A3PN125-ZVQG100 Actel, A3PN125-ZVQG100 Datasheet - Page 61

FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano

A3PN125-ZVQG100

Manufacturer Part Number
A3PN125-ZVQG100
Description
FPGA - Field Programmable Gate Array 125K System Gates ProASIC3 nano
Manufacturer
Actel
Datasheet

Specifications of A3PN125-ZVQG100

Processor Series
A3PN125
Core
IP Core
Number Of Macrocells
1024
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
71
Data Ram Size
36 Kbit
Delay Time
1.02 ns
Supply Voltage (max)
3.3 V
Supply Current
2 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 20 C
Development Tools By Supplier
AGLN-Nano-Kit, AGLN-Z-Nano-Kit, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FloasPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.5 V
Number Of Gates
125 K
Package / Case
VQFP-100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Output DDR Module
Figure 2-17 • Output DDR Timing Model
Table 2-63 • Parameter Definitions
Parameter Name
t
t
t
t
t
t
t
t
DDROCLKQ
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROSUD1
DDROSUD2
DDROHD1
DDROHD2
Data_R
(from core)
Data_F
(from core)
CLK
CLR
Clock-to-Out
Asynchronous Clear-to-Out
Clear Removal
Clear Recovery
Data Setup Data_F
Data Setup Data_R
Data Hold Data_F
Data Hold Data_R
INBUF
CLKBUF
Parameter Definition
D
C
A
B
C
B
X
X
X
X
X
X
R e v i s i o n 8
FF1
FF2
Output DDR
DDR_OUT
0
1
Measuring Nodes (from, to)
E
ProASIC3 nano Flash FPGAs
X
Out
OUTBUF
C, E
C, B
C, B
D, B
D, B
B, E
A, B
A, B
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