HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 101

16BIT MCU FLASH 56K, SMD, LQFP64

HD64F36077GHV

Manufacturer Part Number
HD64F36077GHV
Description
16BIT MCU FLASH 56K, SMD, LQFP64
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F36077GHV

No. Of I/o's
47
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V
Core Size
16bit
Program Memory Size
56KB
Oscillator Type
External Only
Controller Family/series
H8/300H
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
HD64F36077GHV
Manufacturer:
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Quantity:
340
Part Number:
HD64F36077GHV
Manufacturer:
Renesas
Quantity:
200
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
5.2.3
RCTRMDR stores the trimming data of the on-chip oscillator frequency (FSEL = 1, 20 MHz).
Note:
Bit
4
3 to 0
Bit
7
6
5
4
3
2
1
0
*
RC Trimming Data Register (RCTRMDR)
Bit Name
TRMDRWE
Bit Name
TRMD7
TRMD6
TRMD5
TRMD4
TRMD3
TRMD2
TRMD1
TRMD0
These values are initialized to the trimming data loaded from the flash memory.
Initial
Value
0
All 1
Initial
Value
(0)*
(0)*
(0)*
(0)*
(0)*
(0)*
(0)*
(0)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Trimming Data Register Write Enable
This register can be written to when the LOCKDW bit is 0
and this bit is 1.
[Setting condition]
[Clearing conditions]
Reserved
These bits are always read as 1.
Description
Trimming Data (FSEL = 1, 20 MHz)
The trimming data is loaded from the flash memory to this
register right after a reset.
The on-chip oscillator clock (FSEL = 1, 20 MHz) can be
trimmed by changing these bits.
The frequency of the on-chip oscillator clock changes
right after writing these bits. These bits are initialized to
H'00.
Changes in frequency are shown below (bit TRMD7 is a
sign bit).
(Min.) H'80
H'7F (Max.)
When writing 0 to the WRI bit while writing 1 to the
TRMDRWE bit while the PRWE bit is 1
Reset
When writing 0 to the WRI bit and writing 0 to the
TRMDRWE bit while the PRWE bit is 1
H'FF
Rev. 1.00 Sep. 16, 2005 Page 71 of 490
Section 5 Clock Pulse Generator
H'00
REJ09B0216-0100
H'01

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