HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 337

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 16.13 shows a sample flow
chart for serial data reception.
[4]
Yes
Figure 16.13 Sample Serial Reception Flowchart (Clock Synchronous Mode)
No
Read receive data in RDR
Clear OER flag in SSR to 0
Clear RE bit in SCR3 to 0
Read RDRF flag in SSR
Overrun error processing
Read OER flag in SSR
All data received?
Error processing
Start reception
RDRF = 1
OER = 1
<End>
<End>
Yes
No
No
(Continued below)
Error processing
Yes
[1]
[2]
[3]
[4]
Section 16 Serial Communication Interface 3 (SCI3)
[1]
[2]
[3]
[4]
Read the OER flag in SSR to determine if
there is an error. If an overrun error has
occurred, execute overrun error processing.
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR.
When data is read from RDR, the RDRF
flag is automatically cleared to 0.
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag and reading RDR
should be finished. When data is read from
RDR, the RDRF flag is automatically
cleared to 0.
If an overrun error occurs, read the OER
flag in SSR, and after performing the
appropriate error processing, clear the OER
flag to 0. Reception cannot be resumed if
the OER flag is set to 1.
Rev. 1.00 Sep. 16, 2005 Page 307 of 490
REJ09B0216-0100