HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 314

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 16 Serial Communication Interface 3 (SCI3)
16.3.6
SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is
also used to select the transfer clock source. For details on interrupt requests, refer to section 16.7,
Interrupts.
Rev. 1.00 Sep. 16, 2005 Page 284 of 490
REJ09B0216-0100
Bit
7
6
5
4
3
2
Bit Name
TIE
RIE
TE
RE
MPIE
TEIE
Serial Control Register 3 (SCR3)
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
Transmit Enable
When this bit s set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and OER status flags in SSR is disabled.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 16.6, Multiprocessor
Communication Function.
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is enabled.