HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 219

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.6
The following types of contention or operation can occur in timer V operation.
1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear
2. If a compare match is generated in the T3 state of a TCORA or TCORB write cycle, the write
3. If compare matches A and B occur simultaneously, any conflict between the output selections
4. Depending on the timing, TCNTV may be incremented by a switch between different internal
signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing
takes precedence and the write to the counter is not carried out. If counting-up is generated in
the T3 state of a TCNTV write cycle, writing takes precedence.
to TCORA or TCORB takes precedence and the compare match signal is inhibited. Figure
12.12 shows the timing.
for compare match A and compare match B is resolved by the following priority: toggle
output > output 1 > output 0.
clock sources. When TCNTV is internally clocked, an increment pulse is generated from the
falling edge of an internal clock signal, that is divided system clock (φ). Therefore, as shown
in figure 12.3 the switch is from a high clock signal to a low clock signal, the switchover is
seen as a falling edge, causing TCNTV to increment. TCNTV can also be incremented by a
switch between internal and external clocks.
Usage Notes
Figure 12.11 Contention between TCNTV Write and Clear
Counter clear signal
Internal write signal
Address
TCNTV
ø
TCNTV write cycle by CPU
T
1
TCNTV address
N
T
2
Rev. 1.00 Sep. 16, 2005 Page 189 of 490
T
3
H'00
Section 12 Timer V
REJ09B0216-0100