HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 86

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 3 Exception Handling
3.4.2
Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to
enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests
generated by execution of a SLEEP instruction, this function is included in IRR1, IRR2, IENR1,
and IENR2.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. These interrupts can be masked by
writing 0 to clear the corresponding enable bit.
3.4.3
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for
3. The CPU accepts the NMI and address break without depending on the I bit value. Other
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
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signal is sent to the interrupt controller.
the interrupt handling with the highest priority at that time according to table 3.1. Other
interrupt requests are held pending.
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Internal Interrupts
Interrupt Handling Sequence