HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 238

16BIT MCU FLASH 56K, SMD, LQFP64

HD64F36077GHV

Manufacturer Part Number
HD64F36077GHV
Description
16BIT MCU FLASH 56K, SMD, LQFP64
Manufacturer
Renesas Electronics America
Datasheet

Specifications of HD64F36077GHV

No. Of I/o's
47
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V
Core Size
16bit
Program Memory Size
56KB
Oscillator Type
External Only
Controller Family/series
H8/300H
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Part Number:
HD64F36077GHV
Manufacturer:
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Section 13 Timer Z
[Legend] X: Don't care.
TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORC
also selects the function of FTIOC or FTIOD pin.
Rev. 1.00 Sep. 16, 2005 Page 208 of 490
REJ09B0216-0100
Bit
2
1
0
Bit
7
6
5
4
3
Bit Name
IOA2
IOA1
IOA0
Bit Name
IOD2
IOD1
IOD0
Initial
value
0
0
0
Initial
value
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I/O Control A2 to A0
GRA is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRA compare match
010: 1 output by GRA compare match
011: Toggle output by GRA compare match
GRA is an input capture register:
100: Input capture to GRA at the rising edge
101: Input capture to GRA at the falling edge
11X: Input capture to GRA at both rising and falling edges
Reserved
This bit is always read as 1.
I/O Control D2 to D0
GRD is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRD compare match
010: 1 output by GRD compare match
011: Toggle output by GRD compare match
GRD is an input capture register:
100: Input capture to GRD at the rising edge
101: Input capture to GRD at the falling edge
11X: Input capture to GRD at both rising and falling
Reserved
This bit is always read as 1.
Description
Description
edges

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