HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 19

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figures
Section 1 Overview
Figure 1.1 Block Diagram of H8/36077 Group .............................................................................. 3
Figure 1.2 Pin Arrangements of H8/36077 Group (FP-64K, FP-64A)........................................... 4
Section 2 CPU
Figure 2.1 Memory Map............................................................................................................... 10
Figure 2.2 CPU Registers ............................................................................................................. 11
Figure 2.3 Usage of General Registers ......................................................................................... 12
Figure 2.4 Relationship between Stack Pointer and Stack Area ................................................... 13
Figure 2.5 General Register Data Formats (1).............................................................................. 15
Figure 2.5 General Register Data Formats (2).............................................................................. 16
Figure 2.6 Memory Data Formats................................................................................................. 17
Figure 2.7 Instruction Formats...................................................................................................... 28
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 32
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 34
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 35
Figure 2.11 CPU Operation States................................................................................................ 36
Figure 2.12 State Transitions ........................................................................................................ 37
Figure 2.13 Example of Timer Configuration with Two Registers Allocated
to Same Address ........................................................................................................ 38
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 55
Figure 3.2 Stack Status after Exception Handling ........................................................................ 57
Figure 3.3 Interrupt Sequence....................................................................................................... 58
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 59
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 61
Figure 4.2 Address Break Interrupt Operation Example (1)......................................................... 65
Figure 4.2 Address Break Interrupt Operation Example (2)......................................................... 66
Section 5 Clock Pulse Generator
Figure 5.1 Block Diagram of Clock Pulse Generator ................................................................... 67
Figure 5.2 State Transition of System Clock ................................................................................ 75
Figure 5.3 Flowchart of Clock Switching with Backup Function Enabled................................... 76
Figure 5.4 Flowchart of Clock Switching with Backup Function Disabled (1)
(From On-Chip Oscillator Clock to External Clock)................................................... 77
Rev. 1.00 Sep. 16, 2005 Page xix of xxx