HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 360
HD64F36077GHV
Manufacturer Part Number
HD64F36077GHV
Description
16BIT MCU FLASH 56K, SMD, LQFP64
Manufacturer
Renesas Electronics America
Datasheet
1.HD64F36077GHV.pdf
(524 pages)
Specifications of HD64F36077GHV
No. Of I/o's
47
Ram Memory Size
4KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Supply Voltage Range
4.5V
Core Size
16bit
Program Memory Size
56KB
Oscillator Type
External Only
Controller Family/series
H8/300H
Peripherals
ADC
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS
Quantity:
340
Part Number:
HD64F36077GHV
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
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Section 17 I
17.3.4
ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be
transferred, and confirms acknowledge bits to be received.
Rev. 1.00 Sep. 16, 2005 Page 330 of 490
REJ09B0216-0100
Bit
2
1
0
Bit
7
Bit Name
BC2
BC1
BC0
Bit Name
TIE
I
2
2
C Bus Interrupt Enable Register (ICIER)
C Bus Interface 2 (IIC2)
Initial
Value
0
0
0
Initial
Value
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Bit Counter 2 to 0
These bits specify the number of bits to be transferred
next. When read, the remaining number of transfer bits is
indicated. With the I
with one addition acknowledge bit. Bit BC2 to BC0
settings should be made during an interval between
transfer frames. If bits BC2 to BC0 are set to a value
other than 000, the setting should be made while the SCL
pin is low. The value returns to 000 at the end of a data
transfer, including the acknowledge bit. With the clock
synchronous serial format, these bits should not be
modified.
I
000: 9 bits
001: 2 bits
010: 3 bits
011: 4 bits
100: 5 bits
101: 6 bits
110: 7 bits
111: 8 bits
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
2
C Bus Format
2
C bus format, the data is transferred
Clock Synchronous Serial Format
000: 8 bits
001: 1 bits
010: 2 bits
011: 3 bits
100: 4 bits
101: 5 bits
110: 6 bits
111: 7 bits
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