HD64F36077GHV Renesas Electronics America, HD64F36077GHV Datasheet - Page 274

• Manufacturer Part Number: HD64F36077GHV
• Description: 16BIT MCU FLASH 56K, SMD, LQFP64
• Manufacturer: Renesas Electronics America

Specifications of HD64F36077GHV

• No. Of I/o's: 47
• Ram Memory Size: 4KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Supply Voltage Range: 4.5V
• Core Size: 16bit
• Program Memory Size: 56KB
• Oscillator Type: External Only
• Controller Family/series: H8/300H
• Peripherals: ADC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Section 13 Timer Z
When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when
the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been
designated for BR, BR is transferred to GR when the counter is incremented by compare match
A0 or when TCNT_1 is underflowed. If the φ or φ/2 clock is selected by TPSC2 to TPSC0 bits,
the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000. If
the φ/4 or φ/8 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is set to 1.
3. Setting GR Value in Complementary PWM Mode: To set the general register (GR) or modify
Rev. 1.00 Sep. 16, 2005 Page 244 of 490
REJ09B0216-0100
GR during operation in complementary PWM mode, refer to the following notes.
A. Initial value
B. Modifying the setting value
C. Outputting a waveform with a duty cycle of 0% and 100%
a. When other than TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value must be equal to
b. H'0000 to T – 1 (T: Initial value of TCNT0) must not be set for the initial value.
c. GRA_0 – (T – 1) or more must not be set for the initial value.
d. When using buffer operation, the same values must be set in the buffer registers and
a. Writing to GR directly must be performed while the TCNT_1 and TCNT_0 values
b. Do not write the following values to GR directly. When writing the values, a waveform
c. Do not change settings of GRA_0 during operation.
a. Buffer operation is not used and TPSC2 = TPSC1 = TPSC0 = 0
• To output a 0%-duty cycle waveform, write a value equal to or more than the GRA_0
• To output a 100%-duty cycle waveform, write H'0000 while previous GR value<
H'FFFC or less. When TPSC2 = TPSC1 = TPSC0 = 0, the GRA_0 value can be set to
H'FFFF or less.
corresponding general registers.
should satisfy the following expression: H'0000 ≤ TCNT_1 < previous GR value, and
previous GR value < TCNT_0 ≤ GRA_0. Otherwise, a waveform is not output
correctly. For details on outputting a waveform with a duty cycle of 0% and 100%, see
C., Outputting a waveform with a duty cycle of 0% and 100%.
is not output correctly.
H'0000 ≤ GR ≤ T − 1 and GRA_0 − (T − 1) ≤ GR < GRA_0 when TPSC2 = TPSC1 =
TPSC0 = 0
H'0000 < GR ≤ T − 1 and GRA_0 − (T − 1) ≤ GR < GRA_0 + 1 when TPSC2 = TPSC1
= TPSC0 = 0
Write H'0000 or a value equal to or more than the GRA_0 value to GR directly at the
timing shown below.
value while H'0000 ≤ TCNT_1 < previous GR value
TCNT_0 ≤ GRA_0