PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 106

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
FIGURE 9-4:
FIGURE 9-5:
DS39541A-page 106
Data Bus
WR TRIS
WR Port
RBPU
RBx/INTx
Note 1: I/O pins have diode protection to V
Note 1: I/O pin has diode protection to V
2: To enable weak pull-ups, set the appropriate TRIS
(2)
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>).
bit(s) and clear the RBPU bit (INTCON2 register).
RD TRIS
RD Port
TRIS Latch
Data Latch
D
D
CCP2 Input
CK
CK
CCP Enable
RBPU
CCP Output
Schmitt Trigger
Buffer
RB2:RB0 PINS BLOCK
DIAGRAM
RB3 PIN BLOCK DIAGRAM
Enable
CCP Output
WR TRISB
RD PORTB
WR LATB or
WR PORTB
Data Bus
Q
Q
(2)
Q
DD
DD
EN
and V
D
and V
RD TRISB
TTL
Input
Buffer
RD PORTB
RD LATB
TRIS Latch
Data Latch
SS
D
D
V
Advance Information
CK
CK
P
RD Port
SS
DD
.
.
Weak
Pull-up
I/O pin
Q
Q
Q
(1)
Schmitt Trigger
Buffer
Q
1
0
EN
D
V
V
N
P
SS
DD
TTL
Input
Buffer
V
P
2001 Microchip Technology Inc.
DD
Weak
Pull-up
I/O pin
(1)