PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 241

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

MOVLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2001 Microchip Technology Inc.
After Instruction
Decode
WREG
Q1
=
Move literal to WREG
[ label ]
0
k
None
The eight bit literal ’k’ is loaded into
WREG.
1
1
literal ’k’
MOVLW
Read
0000
Q2
0x5A
k
WREG
255
MOVLW k
1110
5Ah
Process
Data
Q3
kkkk
Advance Information
Write to
WREG
Q4
kkkk
MOVWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
WREG
REG
WREG
REG
Q1
PIC18C601/801
=
=
=
=
register ’f’
Move WREG to f
[ label ]
0
a
(WREG)
None
Move data from WREG to register ’f’.
Location ’f’ can be anywhere in the
256 byte Bank. If ’a’ is 0, the Access
Bank will be selected, overriding the
BSR value. If ’a’ is 1, the Bank will
be selected as per the BSR value.
1
1
MOVWF
Read
0110
Q2
4Fh
0FFh
4Fh
4Fh
f
[0,1]
255
MOVWF
111a
REG
f
Process
Data
Q3
DS39541A-page 241
ffff
f [,a]
register ’f’
Write
Q4
ffff