PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 189

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

16.3.2
Once Synchronous Master mode is selected, reception
is enabled by setting either enable bit SREN (RCSTA
register), or enable bit CREN (RCSTA register). Data is
sampled on the RC7/RX/DT pin on the falling edge of
the clock. If enable bit SREN is set, only a single word
is received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
When setting up a Synchronous Master reception, fol-
low these steps:
1.
2.
TABLE 16-9:
FIGURE 16-8:
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception.
INTCON GIE/GIEH PEIE/GIEL
RCREG USART Receive Register
SPBRG Baud Rate Generator Register
RCSTA
TXSTA
Name
2001 Microchip Technology Inc.
PIR1
IPR1
PIE1
RC7/RX/DT pin
RC6/TX/CK pin
Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRGH = ’0’.
Initialize the SPBRG register for the appropriate
baud rate (Section 16.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
(interrupt)
CREN bit
Write to
bit SREN
SREN bit
RCIF bit
RXREG
Read
USART SYNCHRONOUS MASTER
RECEPTION
CSRC
SPEN
Bit 7
—
—
—
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
’0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit0
TMR0IE
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit1
INT0IE
CREN
SYNC
Advance Information
Bit 4
TXIF
TXIE
TXIP
bit2
ADDEN
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
—
bit3
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
Bit 2
Ensure bits CREN and SREN are clear.
If interrupts are desired, set enable bit RCIE.
If 9-bit reception is desired, set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
the enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bit4
TMR2IF
TMR2IE
TMR2IP
INT0IF
OERR
TRMT
Bit 1
bit5
PIC18C601/801
TMR1IE
TMR1IP
TMR1IF
RX9D
TX9D
RBIF
Bit 0
bit6
0000 000x
-000 0000
-000 0000
-000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
Value on
POR,
BOR
bit7
DS39541A-page 189
Value on all
Q1 Q2 Q3 Q4
0000 000u
-000 0000
-000 0000
-000 0000
0000 -00x
0000 0000
0000 0010
0000 0000
RESETS
other
’0’