PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 246

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS39541A-page 246
After Interrupt
operation
Decode
PC
WREG
BSR
STATUS
GIE/GIEH, PEIE/GIEL
No
Q1
operation
operation
Return from Interrupt
[ label ]
s
(TOS)
1
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged.
None
Return from Interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting the either the
high or low priority global interrupt
enable bit. If ’s’ = 1, the contents
of the shadow registers WS,
STATUSS and BSRS are loaded
into their corresponding registers,
WREG, STATUS and BSR. If
’s’ = 0, no update of these
registers occurs (default).
1
2
RETFIE
0000
No
No
Q2
[0,1]
GIE/GIEH or PEIE/GIEL,
WREG,
PC,
1
RETFIE [s]
0000
BSR,
operation
operation
=
=
=
=
=
No
No
STATUS,
Q3
TOS
WS
BSRS
STATUSS
1
0001
Set GIEH or
from stack
Advance Information
operation
Pop PC
GIEL
No
Q4
000s
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
TABLE
CALL TABLE
:
ADDWF PCL
RETLW k0
RETLW k1
:
:
RETLW kn
Before Instruction
After Instruction
operation
Decode
WREG
WREG
No
Q1
; WREG contains table
;
;
;
; WREG = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to WREG
[ label ]
0
k
(TOS)
PCLATU, PCLATH are unchanged
None
W is loaded with the eight-bit literal
'k'. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
1
2
literal ’k’
Read
No
0000
offset value
WREG now has
table value
Q2
07h
value of kn
k
W,
2001 Microchip Technology Inc.
255
PC,
RETLW k
1100
operation
Process
Data
No
Q3
kkkk
stack, write to
Pop PC from
operation
WREG
No
Q4
kkkk