PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 58
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC](/photos/12/13/121359/c04-093_l_sml.jpg)
PIC18C801-I/L
Manufacturer Part Number
PIC18C801-I/L
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C801-I/L
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
84-PLCC
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
47
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C801-I/LR
PIC18C801-I/LR
PIC18C801I/L
PIC18C801-I/LR
PIC18C801I/L
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C801-I/L
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C801-I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 58 of 320
- Download datasheet (6Mb)
PIC18C601/801
4.10
The Access Bank is an architectural enhancement that
is very useful for C compiler code optimization. The
techniques used by the C compiler are also useful for
programs written in assembly.
This data memory region can be used for:
• Intermediate computational values
• Local variables of subroutines
• Faster context saving/switching of variables
• Common variables
• Faster evaluation/control of SFR’s (no banking)
The Access Bank is comprised of the upper 128 bytes
in Bank 15 (SFR’s) and the lower 128 bytes in Bank 0.
These two sections will be referred to as Access Bank
High and Access Bank Low, respectively. Figure 4-8
indicates the Access Bank areas.
A bit in the instruction word specifies if the operation is
to occur in the bank specified by the BSR register, or in
the Access Bank.
When forced in the Access Bank (a = ’0’), the last
address in Access Bank Low is followed by the first
address in Access Bank High. Access Bank High maps
all Special Function Registers so that these registers
can be accessed without any software overhead.
FIGURE 4-10:
DS39541A-page 58
Note 1: For register file map detail, see Table 4-2.
Access Bank
bank select
2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the
3: The MOVFF instruction embeds the entire 12-bit address in the instruction.
registers of the Access Bank.
BSR<3:0>
(2)
DIRECT ADDRESSING
location select
7
Direct Addressing
Data
Memory
from opcode
Advance Information
(1)
(3)
(3)
000h
0FFh
Bank 0
00h
4.11
The need for a large general purpose memory space
dictates a RAM banking scheme. When using direct
addressing, the BSR should be configured for the
desired bank.
BSR<3:0> holds the upper 4 bits of the 12-bit RAM
address. The BSR<7:4> bits will always read ’0’s, and
writes will have no effect.
A MOVLB instruction has been provided in the instruc-
tion set to assist in selecting banks.
If the currently selected bank is not implemented, any
read will return all '0's and all writes are ignored. The
STATUS register bits will be set/cleared as appropriate
for the instruction performed.
Each Bank extends up to 0FFh (256 bytes). All data
memory is implemented as static RAM.
A MOVFF instruction ignores the BSR, since the 12-bit
addresses are embedded into the instruction word.
Section 4.12 provides a description of indirect address-
ing, which allows linear addressing of the entire RAM
space.
0
100h
1FFh
Bank 1
01h
Bank Select Register (BSR)
E00h
EFFh
2001 Microchip Technology Inc.
Bank 14
0Eh
F00h
FFFh
Bank 15
0Fh
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