PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 64

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
5.2
The External Memory Interface can operate in 8-bit
mode. The mode selection is not software configurable,
but is programmable via the configuration bits.
There are two types of connections in 8-bit mode. They
are referred to as:
• 8-bit Multiplexed
• 8-bit De-Multiplexed
5.2.1
The 8-bit Multiplexed mode applies only to the
PIC18C601. Data and address lines are multiplexed on
port pins and must be decoded with glue logic.
For 8-bit Multiplexed mode on the PIC18C601, the
instructions will be fetched as two 8-bit bytes on a
shared data/address bus (PORTD). The two bytes are
sequentially fetched within one instruction cycle (T
FIGURE 5-1:
TABLE 5-1:
DS39541A-page 64
RG2/WRL
RF3/CSIO
RG0/ALE
RG4/BA0
RF5/CS1
RG1/OE
8-bit Mode
Name
Note 1: This signal only applies to Table Writes. See Section 6.0, Table Reads and Writes.
8-BIT MULTIPLEXED MODE
PIC18C601
A16, AD<15:8>
8-BIT MULTIPLEXED MODE CONTROL SIGNALS
AD<7:0>
8-BIT MULTIPLEXED MODE EXAMPLE
WRL
ALE
BA0
CS1
OE
8-bit Mux
Mode
CSIO
WRL
ALE
BA0
CS1
OE
Advance Information
CY
Address Latch Enable (ALE) control pin
Output Enable (OE) control pin
Write Low (WRL) control pin
Byte address bit 0
Chip Select I/O (See Section 5.4)
Chip Select 1 (See Section 5.4)
).
373
Therefore, the designer must choose external memory
devices according to timing calculations based on 1/2
Tcy (2 times instruction rate). For proper memory
speed selection, glue logic propagation delay times
must be considered along with setup and hold times.
The Address Latch Enable (ALE) pin indicates that the
address bits A<7:0> are available on the External
Memory Interface bus. The OE output enable signal will
enable one byte of program memory for a portion of the
instruction cycle, then BA0 will change and the second
byte will be enabled to form the 16-bit instruction word.
The least significant bit of the address, BA0, must be
connected to the memory devices in this mode.
Figure 5-1 shows an example of 8-bit Multiplexed
mode on the PIC18C601. The control signals used in
8-bit Multiplexed mode are outlined in Table 5-1.
Register 5-2 describes 8-bit Multiplexed mode timing.
A<17:0>
D<7:0>
Function
2001 Microchip Technology Inc.
A<x:1>
D<7:0>
A0
CE
OE WR
(2)