PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 94

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
8.1.2
The Peripheral Interrupt Request (PIR) registers con-
tain the individual flag bits for the peripheral interrupts
(Register 8-5). There are two Peripheral Interrupt
Request (Flag) registers (PIR1, PIR2).
REGISTER 8-4:
DS39541A-page 94
Note 1: Interrupt flag bits are set when an interrupt
2: User software should ensure the appropri-
PIR REGISTERS
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON register).
ate interrupt flag bits are cleared prior to
enabling an interrupt, and after servicing
that interrupt.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
RCON REGISTER
bit 7
IPEN: Interrupt Priority Enable bit
1 = Enable priority levels on interrupts
0 = Disable priority levels on interrupts (16CXXX compatibility mode)
Reserved: Maintain as '0'
Unimplemented: Read as '0'
RI: RESET Instruction Flag bit
For details of bit operation, see Register 4-4
TO: Watchdog Time-out Flag bit
For details of bit operation, see Register 4-4
PD: Power-down Detection Flag bit
For details of bit operation, see Register 4-4
POR: Power-on Reset Status bit
For details of bit operation, see Register 4-4
Reserved: Maintain as '0'
Legend:
R = Readable bit
- n = Value at POR
R/W-0
IPEN
U-0
r
Advance Information
U-0
W = Writable bit
’1’ = Bit is set
—
R/W-1
8.1.3
The Peripheral Interrupt Enable (PIE) registers contain
the individual enable bits for the peripheral interrupts
(Register 8-6). There are two two Peripheral Interrupt
Enable registers (PIE1, PIE2). When IPEN is clear, the
PEIE bit must be set to enable any of these peripheral
interrupts.
8.1.4
The Interrupt Priority (IPR) registers contain the individ-
ual priority bits for the peripheral interrupts (Register 8-9).
There are two Peripheral Interrupt Priority registers
(IPR1, IPR2). The operation of the priority bits requires
that the Interrupt Priority Enable bit (IPEN) be set.
8.1.5
The Reset Control (RCON) register contains the bit that
is used to enable prioritized interrupts (IPEN).
RI
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-1
PIE REGISTERS
IPR REGISTERS
RCON REGISTER
TO
R/W-1
PD
2001 Microchip Technology Inc.
x = Bit is unknown
R/W-0
POR
U-0
r
bit 0