PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 55

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

TABLE 4-2:
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FCFh
FCEh
FCDh
FCCh
FCBh
FCAh
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
FBFh
FBEh
FBDh
FBCh
FBBh
FBAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
Legend
Note 1: Other (non-power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
2001 Microchip Technology Inc.
File Name
2: These registers can only be modified when the Combination Lock is open.
3: These registers are available on PIC18C801 only.
TMR0H
TMR0L
T0CON
Reserved
OSCCON
LVDCON
WDTCON
RCON
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
ADCON2
CCPR1H
CCPR1L
CCP1CON
CCPR2H
CCPR2L
CCP2CON
Reserved
Reserved
Reserved
TMR3H
TMR3L
T3CON
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved
(2)
(2)
(2)
REGISTER FILE SUMMARY - PIC18C601/801 (CONTINUED)
Capture/Compare/PWM Register1 Low Byte
Capture/Compare/PWM Register2 Low Byte
Timer0 Register High Byte
Timer0 Register Low Byte
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register1 High Byte
Capture/Compare/PWM Register2 High Byte
Timer3 Register High Byte
Timer3 Register Low Byte
TMR0ON
WCOL
GCEN
ADFM
RD16
RD16
IPEN
Bit 7
SMP
—
—
—
—
—
—
—
—
TOUTPS3
ACKSTAT
T3CCP2
SSPOV
16BIT
Bit 6
CKE
—
—
—
—
—
—
—
—
—
r
2
C Slave Mode. SSP Baud Rate Reload Register in I
T1CKPS1
TOUTPS2
T3CKPS1
SSPEN
ACKDT
VCFG1
DC1B1
DC2B1
IRVST
T0CS
CHS3
Bit 5
D/A
—
—
—
—
Advance Information
TOUTPS1 TOUTPS0
T1CKPS0 T1OSCEN
T3CKPS0
ACKEN
VCFG0
LVDEN
DC1B0
DC2B0
CHS2
T0SE
Bit 4
CKP
—
—
RI
—
P
CCP1M3
CCP2M3
T3CCP1
WDPS2
SSPM3
PCFG3
T0PS3
RCEN
LOCK
CHS1
LVV3
Bit 3
TO
—
S
TMR2ON
CCP1M2
CCP2M2
T1SYNC
T3SYNC
WDPS1
SSPM2
PCFG2
ADCS2
PLLEN
T0PS2
CHS0
LVV2
Bit 2
R/W
PEN
PD
PIC18C601/801
2
GO/DONE
T2CKPS1
C Master Mode
TMR1CS
CCP1M1
CCP2M1
TMR3CS
WDPS0
SSPM1
PCFG1
ADCS1
T0PS1
RSEN
SCS1
LVV1
Bit 1
POR
UA
SWDTEN ---- 0000 ---- xxxx
TMR1ON 0-00 0000 u-uu uuuu
T2CKPS0 -000 0000 -000 0000
TMR3ON 0000 0000 uuuu uuuu
CCP1M0 --00 0000 --00 0000
CCP2M0 --00 0000 --uu uuuu
SSPM0
PCFG0
ADCS0
T0PS0
ADON
SCS0
LVV0
Bit 0
SEN
BF
r
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
1111 1111 1111 1111
rrrr rrrr rrrr rrrr
---- 0000 ---- uuu0
--00 0101 --00 0101
00-1 11qq 00-q qquu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
--00 0000 --00 0000
0--- -000 0--- -000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
rrrr rrrr rrrr rrrr
rrrr rrrr rrrr rrrr
rrrr rrrr rrrr rrrr
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
DS39541A-page 55
Value on
POR
RESETS
Value on
all other
(1)