PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 215

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

20.0
The PIC18C601/801 instruction set adds many
enhancements to the previous PICmicro
sets, while maintaining an easy migration path from
them.
With few exceptions, instructions are a single program
memory word (16-bits). Each single word instruction is
divided into an OPCODE, which specifies the instruc-
tion type, and one or more operands which further
specify the operation of the instruction.
The instruction set is highly orthogonal and is grouped
into four basic categories:
• Byte-oriented operations
• Bit-oriented operations
• Literal operations
• Control operations
The PIC18C601/801 instruction set summary in
Table 20-2 lists byte-oriented, bit-oriented, literal
and control operations. Table 20-1 shows the opcode
field descriptions.
Most byte-oriented instructions have three operands:
1.
2.
3.
The file register designator ‘f’ specifies which file regis-
ter is to be used by the instruction.
The destination designator ‘d’ specifies where the
result of the operation is to be placed. If 'd' is zero, the
result is placed in the WREG register. If 'd' is one, the
result is placed in the file register specified in the
instruction.
All bit-oriented instructions have three operands:
1.
2.
3.
The bit field designator 'b' selects the number of the bit
affected by the operation, while the file register desig-
nator 'f' represents the number of the file in which the
bit is located.
2001 Microchip Technology Inc.
The file register (represented by ’f’)
The destination of the result
(represented by ’d’)
The accessed memory
(represented by ’a’)
The file register (represented by ’f’)
The bit in the file register
(represented by ’b’)
The accessed memory
(represented by ’a’)
INSTRUCTION SET SUMMARY
®
Advance Information
instruction
The literal instructions may use some of the following
operands:
• A literal value to be loaded into a file register
• The desired FSR register to load the literal value
• No operand required
The control instructions may use some of the following
operands:
• A program memory address (represented by ’n’)
• The mode of the Call or Return instructions
• The mode of the Table Read and Table Write
• No operand required
All instructions are a single word, except for four double
word instructions. These four instructions were made
double word instructions so that all the required infor-
mation is available in these 32 bits. In the second word,
the 4 MSbs are 1’s. If this second word is executed as
an instruction (by itself), it will execute as a NOP.
All single word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles, with the additional instruction cycle(s) executed
as a NOP.The double word instructions execute in two
instruction cycles.
One instruction cycle consists of four oscillator periods.
Thus, for an oscillator frequency of 4 MHz, the normal
instruction execution time is 1 s. If a conditional test is
true, or the program counter is changed as a result of
an instruction, the instruction execution time is 2 s.
Two word branch instructions (if true) would take 3 s.
Figure 20-1 shows the general formats that the instruc-
tions can have. All examples use the format ‘nnh’ to
represent a hexadecimal number, where ‘h’ signifies
a hexadecimal digit.
The Instruction Set Summary, shown in Table 20-2,
lists the instructions recognized by the Microchip
assembler (MPASM
Section 20.1 provides a description of each instruction.
(represented by ’k’)
into (represented by ’f’)
(specified by ’—’)
(represented by ’s’)
instructions (represented by ’m’)
(specified by ’—’)
PIC18C601/801
TM
).
DS39541A-page 215