PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 119

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

9.7
PORTG is a 5-bit wide, bi-directional port. The corre-
sponding data direction register is TRISG. Setting a
TRISG bit (= 1) will make the corresponding PORTG
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISG bit (= 0) will
make the corresponding PORTG pin an output (i.e., put
the contents of the output latch on the selected pin).
Read-modify-write operations on the LATG register
read and write the latched output value for PORTG.
PORTG is multiplexed with system bus control signals
ALE, OE, WRH, WRL and BA0. The WRH signal is the
only signal that is disabled and configured as a port pin
(RG3) during external program execution in 8-bit mode.
All other pins are by default, system bus control sig-
nals. PORTG can be configured as an I/O port by set-
ting EBDIS bit in the MEMCON register and when
execution is taking place in internal program RAM.
EXAMPLE 9-8:
CLRF
CLRF
MOVLW
MOVWF
Note:
2001 Microchip Technology Inc.
PORTG, LATG, and TRISG
Registers
PORTG
LATG
04h
TRISG
On Power-on Reset, PORTG defaults to
system bus signals.
INITIALIZING PORTG
; Initialize PORTG by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RG1:RG0 as outputs
; RG2 as input
; RG4:RG3 as outputs
Advance Information
FIGURE 9-14:
WR TRISG
WR LATG
or
PORTG
Note 1: I/O pins have diode protection to V
Data
Bus
RD PORTG
PIC18C601/801
Data Latch
TRIS Latch
RD LATG
D
D
CK
CK
RD TRISG
Q
PORTG BLOCK DIAGRAM
IN I/O MODE
Q
Q
EN
EN
Schmitt
Trigger
Input
Buffer
DS39541A-page 119
D
DD
and V
I/O pin
SS
.
(1)