PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 25

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

REGISTER 2-1:
2.6.2
PIC18C601/801 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-6.
The Timer1 oscillator is assumed to be running all the
time. After the SCS0 bit is set, the processor is frozen
at the next occurring Q1 cycle. After eight synchroniza-
tion cycles are counted from the Timer1 oscillator, oper-
ation resumes. No additional delays are required after
the synchronization cycles.
2001 Microchip Technology Inc.
bit 7-4
bit 3
bit 2
bit 1
bit 0
OSCILLATOR TRANSITIONS
OSCCON REGISTER
Unimplemented: Read as '0'
LOCK: Phase Lock Loop Lock Status bit
1 = Phase Lock Loop output is stable as system clock
0 = Phase Lock Loop output is not stable and cannot be used as system clock
PLLEN: Phase Lock Loop Enable bit
1 = Enable Phase Lock Loop output as system clock
0 = Disable Phase Lock Loop
SCS1: System Clock Switch bit 1
When PLLEN and LOCK bit are set:
1 = Use PLL output
0 = Use primary oscillator/clock input pin
When PLLEN bit or LOCK bit is cleared:
Bit is forced clear
SCS0: System Clock Switch bit 0
When T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When T1OSCEN is cleared:
Bit is forced clear
bit 7
Legend:
R = Readable bit
- n = Value at POR
U-0
—
U-0
—
Advance Information
U-0
—
W = Writable bit
’1’ = Bit is set
U-0
—
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crys-
tal (HS, LP), the transition will take place after an oscil-
lator start-up time (T
diagram indicating the transition from the Timer1 oscil-
lator to the main oscillator for HS and LP modes is
shown in Figure 2-7.
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R/W-0
LOCK
PIC18C601/801
OST
PLLEN
R/W-0
) has occurred. A timing
x = Bit is unknown
R/W-0
SCS1
DS39541A-page 25
R/W-0
SCS0
bit 0