PIC18C801-I/L Microchip Technology, PIC18C801-I/L Datasheet - Page 30

• Manufacturer Part Number: PIC18C801-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,84PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C801-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 84-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164310 - MODULE SKT FOR PM3 84PLCCXLT84L1 - SOCKET TRANSITION ICE 84PLCCAC174012 - MODULE SKT PROMATEII 84PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C801-I/LR; PIC18C801-I/LR; PIC18C801I/L

PIC18C601/801
3.1
A Power-on Reset pulse is generated on-chip when a
V
cuitry, connect the MCLR pin directly (or through a
resistor) to V
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for V
eter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met. Power-on Reset may be used to meet
the voltage start-up condition.
FIGURE 3-2:
3.2
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. The PWRT time delay allows V
acceptable level. PIC18C601/801 devices are avail-
able with PWRT enabled or disabled.
The power-up time delay will vary from chip to chip, due
to V
parameter #33 for details.
DS39541A-page 30
DD
Note 1: External Power-on Reset circuit is required only
DD
rise is detected. To take advantage of the POR cir-
, temperature and process variation. See DC
2: R < 40 k
3: R1 = 100
Power-on Reset (POR)
Power-up Timer (PWRT)
if the V
D helps discharge the capacitor quickly when
V
the voltage drop across R does not violate the
device’s electrical specification.
into MCLR from external capacitor C, in the
event of MCLR/V
Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).
D
DD
DD
V
powers down.
. This will eliminate external RC compo-
DD
DD
R
C
power-up slope is too slow. The diode
is recommended to make sure that
to 1 k
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
R1
PP
will limit any current flowing
pin breakdown due to
DD
PIC18C601/801
DD
MCLR
is specified (param-
POWER-UP)
DD
to rise to an
Advance Information
3.3
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter #32). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for LP, HS and HS4
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4
With the PLL enabled, the time-out sequence following
a Power-on Reset is different from other oscillator
modes. A portion of the Power-up Timer is used to pro-
vide a fixed time-out that is sufficient for the PLL to lock
to the main oscillator frequency. This PLL lock time-out
(T
up time-out (OST).
3.5
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired; then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of the PWRT. For example, in RC mode with
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18C601/801 device
operating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all registers.
PLL
) is typically 1 ms and follows the oscillator start-
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Time-out Sequence
2001 Microchip Technology Inc.