LAN9311I-NZW Standard Microsystem (Smsc), LAN9311I-NZW Datasheet - Page 197

• Manufacturer Part Number: LAN9311I-NZW
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311I-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2.3.4
31:10
BITS
9:8
7:0
RESERVED
LED Function 1-0 (LED_FUN[1:0])
These bits control the function associated with each LED pin as shown in
Table 13.1
Note:
LED Enable 7-0 (LED_EN[7:0])
This field toggles the functionality of the GPIO[7:0] pins between GPIO and
LED.
0: Enables the associated pin as a GPIO signal
1: Enables the associated pin as a LED output
LED Configuration Register (LED_CFG)
This read/write register configures the GPIO[7:0] pins as LED[7:0] pins and sets their functionality.
Note 14.2 The default value of this field is determined by the configuration strap LED_fun_strap[1:0].
Note 14.3 The default value of this field is determined by the configuration strap LED_en_strap[7:0].
In order for these assignments to be valid, the particular pin must
be enabled as an LED output pin via the LED_EN[7:0] bits of this
register.
of
Offset:
Section 13.3, "LED Operation," on page
Configuration strap values are latched on power-on reset or nRST de-assertion. Some
configuration straps can be overridden by values from the EEPROM Loader. Refer to
Section 4.2.4, "Configuration Straps," on page 40
Configuration strap values are latched on power-on reset or nRST de-assertion. Some
configuration straps can be overridden by values from the EEPROM Loader. Refer to
Section 4.2.4, "Configuration Straps," on page 40
1BCh
DESCRIPTION
DATASHEET
197
Size:
165.
for more information.
for more information.
32 bits
TYPE
R/W
R/W
RO
Revision 1.7 (06-29-10)
DEFAULT
Note 14.2
Note 14.3
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