LAN9311I-NZW Standard Microsystem (Smsc), LAN9311I-NZW Datasheet - Page 254

• Manufacturer Part Number: LAN9311I-NZW
• Manufacturer: Standard Microsystem (Smsc)

Specifications of LAN9311I-NZW

• Package: 128XVTQFP
• Phy/transceiver Interface: MII
• Number Of Primary Switch Ports: 2
• Maximum Data Rate: 100 Mbps
• Internal Memory Buffer Size: 32 KB
• Vlan Support: Yes
• Power Supply Type: Analog
• Minimum Single Supply Voltage: 3 V
• Maximum Single Supply Voltage: 3.6 V
• Maximum Supply Current: 0.295 A
• Maximum Power Dissipation: 1070 mW

Revision 1.7 (06-29-10)
BITS
4:0
5
10BASE-T Half Duplex
This bit determines the advertised 10BASE-T half duplex capability.
0: 10BASE-T half duplex ability not advertised
1: 10BASE-T half duplex ability advertised
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001: IEEE 802.3
Note 14.27 The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
Note 14.28 The Virtual PHY does not support next page capability. This bit value will always be 0.
Note 14.29 The Remote Fault bit is not useful since there is no actual link partner to send a fault to.
Note 14.30 The Pause bit defaults to 1 if the manual_FC_strap_mii strap is low, and 0 if the
Note 14.31 Virtual 100BASE-T4 is not supported.
Note 14.32 The Virtual PHY supports only IEEE 802.3. Only a value of 00001b should be used in this
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.
manual_FC_strap_mii strap is high. Configuration strap values are latched upon the de-
assertion of a chip-level reset as described in
page
field.
40.
DESCRIPTION
DATASHEET
254
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Section 4.2.4, "Configuration Straps," on
TYPE
R/W
R/W
SMSC LAN9311/LAN9311i
Note 14.32
DEFAULT
00001b
Datasheet
1b