CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet

IC ADC STEREO 24BIT 98DB 32QFN

CS53L21-CNZ

Manufacturer Part Number
CS53L21-CNZ
Description
IC ADC STEREO 24BIT 98DB 32QFN
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS53L21-CNZ

Package / Case
32-QFN
Number Of Converters
2
Number Of Bits
24
Sampling Rate (per Second)
100k
Data Interface
Serial
Power Dissipation (max)
30mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
96 KSPS
Resolution
24 bit
Number Of Adc Inputs
6
Operating Supply Voltage
1.8 V or 2.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 10 C
Mounting Style
SMD/SMT
Power Consumption
60 mW
Supply Voltage (max)
2.63 V
Supply Voltage (min)
1.65 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1550 - BOARD EVAL FOR CS53L21 ADC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1191

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS53L21-CNZ
Manufacturer:
Cirrus
Quantity:
13 781
Part Number:
CS53L21-CNZR
Manufacturer:
CIRRUS
Quantity:
20 000
Preliminary Product Information
FEATURES
Software Mode
Control Data
Hardware Mode
or I
Serial Audio
2
98 dB Dynamic Range (A-wtd)
-88 dB THD+N
Analog Gain Controls
+20 dB Digital Boost
Programmable Automatic Level Control (ALC)
Independent Left/Right Channel Control
Digital Volume Control
High-Pass Filter Disable for DC Measurements
Stereo 3:1 Analog Input MUX
Dual MIC Inputs
Very Low 64 Fs Oversampling Clock Reduces
Power Consumption
C & SPI
http://www.cirrus.com
Output
Reset
+32 dB or +16 dB MIC Pre-Amplifiers
Analog Programmable Gain Amplifier
(PGA)
Noise Gate for Noise Suppression
Programmable Threshold and
Attack/Release Rates
Programmable, Low Noise MIC Bias Levels
Differential MIC Mix for Common Mode
Noise Rejection
Low Power, Stereo Analog to Digital Converter
1.8 V to 3.3 V
High Pass
Processing
Engine
Filters
Digital
Signal
Configuration
Register
1.8 V to 2.5 V
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
ALC
ALC
Copyright © Cirrus Logic, Inc. 2006
Controls
Volume
(All Rights Reserved)
SYSTEM FEATURES
Oversampling
Oversampling
24-bit Conversion
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Operation
Variable Power Supplies
Power Down Management
Software Mode (I²C
Hardware Mode (Stand-Alone Control)
Flexible Clocking Options
Digital Routing Mixes
Multibit
Multibit
ADC
ADC
Stereo Record (ADC): 8.72 mW @ 1.8 V
Stereo Record (MIC to PGA and ADC):
13.73 mW @ 1.8 V
1.8 V to 2.5 V Digital & Analog
1.8 V to 3.3 V Interface Logic
ADC, MIC Pre-Amplifier, PGA
Master or Slave Operation
Mono Mixes
MUX
MUX
PGA
PGA
®
MUX
& SPI
CS53L21
MIC
Bias
+32 dB
+32 dB
Control)
Stereo Input 1
Stereo Input 2
Stereo Input 3 /
Mic Input 1 & 2
DS700PP1
MAY ‘06

Related parts for CS53L21-CNZ

CS53L21-CNZ Summary of contents

Page 1

... This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) CS53L21 Stereo Record (ADC): 8. 1.8 V Stereo Record (MIC to PGA and ADC): 13. 1 2.5 V Digital & Analog 1 ...

Page 2

... Voice Recognition Systems Audio/Video Capture Cards 2 GENERAL DESCRIPTION The CS53L21 is a highly integrated, 24-bit, 96 kHz, low power stereo A/D. Based on multi-bit, delta-sigma mod- ulation, it allows infinite sample rate adjustment between 4 kHz and 96 kHz. The ADC offers many fea- tures suitable for low power, portable system applications ...

Page 3

... Digital Interface Formats ................................................................................................................ 31 4.7 Initialization ..................................................................................................................................... 32 4.8 Recommended Power-Up Sequence ............................................................................................. 32 4.9 Recommended Power-Down Sequence ........................................................................................ 33 4.10 Software Mode ............................................................................................................................. 34 4.10.1 SPI Control .......................................................................................................................... 34 4.10.2 I²C Control ........................................................................................................................... 34 4.10.3 Memory Address Pointer (MAP) .......................................................................................... 36 4.10.3.1 Map Increment (INCR) ............................................................................................. 36 5. REGISTER QUICK REFERENCE ........................................................................................................ 37 6. REGISTER DESCRIPTION .................................................................................................................. 40 DS700PP1 CS53L21 3 ...

Page 4

... Figure 12.Signal Processing Engine ......................................................................................................... 28 Figure 13.Master Mode Timing ................................................................................................................. 30 Figure 14.Tri-State Serial Port .................................................................................................................. 31 Figure 15.I²S Format ................................................................................................................................. 31 Figure 16.Left-Justified Format ................................................................................................................. 32 Figure 17.Initialization Flow Chart ............................................................................................................. 33 Figure 18.Control Port Timing in SPI Mode .............................................................................................. 34 Figure 19.Control Port Timing, I²C Write ................................................................................................... 35 Figure 20.Control Port Timing, I²C Read ................................................................................................... 35 4 CS53L21 DS700PP1 ...

Page 5

... Figure 21.AIN & PGA Selection ................................................................................................................ 47 Figure 22.ADC THD+N vs. Frequency w/Capacitor Effects ...................................................................... 56 Figure 23.ADC Passband Ripple .............................................................................................................. 60 Figure 24.ADC Stopband Rejection .......................................................................................................... 60 Figure 25.ADC Transition Band ................................................................................................................ 60 Figure 26.ADC Transition Band Detail ...................................................................................................... 60 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Mode Feature Summary ............................................................................................. 21 Table 3. MCLK/LRCK Ratios .................................................................................................................... 30 DS700PP1 CS53L21 5 ...

Page 6

... Analog Ground (Input) - Ground reference for the internal analog section. Test Out (Output) - This pin is an output used for test purposes only and must be left “floating” (no con- 8 TSTO nection external to the pin CS53L21 Pin Description CS53L21 AIN1B 24 AIN1A 23 AFILTB 22 AFILTA 21 AIN2B/BIAS 20 AIN2A 19 MICIN2/BIAS/AIN3B 18 MICIN1/AIN3A 17 DS700PP1 ...

Page 7

... Serial Clock (Input/Output) -- Serial clock for the serial audio interface. Test In (Input) - This pin is an input used for test purposes only and should be tied to DGND for normal 32 TSTN operation. - Thermal Pad Thermal relief pad for optimized heat dissipation. See DS700PP1 CS53L21 “QFN Thermal Pad” on page 59. 7 ...

Page 8

... LRCK Input/Output SCLK Input/Output SDOUT Input/Output (M/S) 8 Driver - - 1 3.3 V, CMOS/Open Drain - - 1 3.3 V, CMOS 1 3.3 V, CMOS 1 3.3 V, CMOS Table 1. I/O Power Rails CS53L21 Receiver 1 3 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3 3 3 3 3.3 V DS700PP1 ...

Page 9

... AIN3B/MICIN2 0.1 µF VL FILT+ AGND * 150 pF AFILTA AFILTB VQ * Capacitors must be C0G or equivalent DGND CS53L21 See Note 4 +1 +2.5 V Note 4: Series resistance in the path of the power supplies must be avoided. Left Analog Input 1 100 Ω 1 µF 100 kΩ 100 kΩ 100 Ω Right Analog Input 1 1 µ ...

Page 10

... I²S/LJ FILT+ MCLKDIV2 AGND * 150 pF AFILTA VL AFILTB VQ * Capacitors must be C0G or equivalent DGND CS53L21 See Note 4 +1.8V or +2.5V Note 4: Series resistance in the path of the power supplies (typically used for added filtering) must be avoided. Left Analog Input 1 100 Ω µF 100 kΩ * 100 kΩ ...

Page 11

... The maximum over/under voltage is limited by the input current. DS700PP1 Symbol Commercial - CNZ T A Automotive - DNZ Symbol VA Analog VD Digital VL Serial/Control Port Interface I (Note (Note IND stg CS53L21 Min Nom Max Units 1.65 1.8 1.89 V 2.37 2.5 2.63 V 1.65 1.8 1.89 V 2.37 2.5 2.63 V 1.65 1.8 1.89 V 2.37 2.5 2. ...

Page 12

... ADC 0.75•VA 0.794•VA 0.83•VA PGA (0 dB) 0.129•VA MIC (+16 dB) 0.022•VA MIC (+32 dB ADC - 39 PGA - 50 MIC CS53L21 VA = 1.8 V (nominal) Max Min Typ Max - -80 - - ...

Page 13

... PGA to ADC - 78 A-weighted - 74 unweighted - -74 -1 dBFS - 0.1 - ±100 - 352 - 90 0.74•VA 0.78•VA 0.82•VA ADC 0.75•VA 0.794•VA 0.83•VA PGA (0 dB) 0.129•VA 0.022• ADC 40 - PGA 50 - MIC CS53L21 VA = 1.8 V (nominal) Min Typ Max - -78 - - ...

Page 14

... SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge 14 (Note 6) to -0.1 dB corner = 15 pF.) LOAD Symbol (Note 7) (Note 8) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode t s(LK-SK) t d(MSB) t s(SDO-SK) t h(SK-SDO) CS53L21 Min Typ Max Unit 0 - 0.4948 Fs -0.09 - 0. ...

Page 15

... LRCK Edge to SDOUT MSB Output Delay SDOUT Setup Time Before SCLK Rising Edge SDOUT Hold Time After SCLK Rising Edge 7. After powering up the CS53L21, RESET should be held low after the power supplies and clocks are settled. 8. See “Example System Clock Frequencies” on page 57 9. See“ ...

Page 16

... Repeated Start Start t high t hdst sud t sust low hdd Figure 5. Control Port Timing - I²C CS53L21 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 3450 , of SCL. fc Stop susp ...

Page 17

... For f <1 MHz. sck RST CS CCLK CDIN DS700PP1 Symbol f sck t srs t css t csh t scl t sch t dsu t (Note 12 (Note 13 (Note 13 srs css sch scl dsu dh Figure 6. Control Port Timing - SPI Format CS53L21 Min Max Units 0 6.0 MHz μs 1 100 ns - 100 ns t csh ...

Page 18

... OL High-Level Input Voltage Low-Level Input Voltage 16. See “Digital I/O Pin Characteristics” on page 8 18 MICBIAS_LVL[1: MICBIAS_LVL[1: MICBIAS_LVL[1: MICBIAS_LVL[1: kHz 1 kHz (Note 15) 1 kHz (Note 16) Symbol for serial and control port power rails. CS53L21 Min Typ Max - 0.5• 0.8•VA ...

Page 19

... RESET pin 25 held HI, all clocks and data lines are held HI. 20. VL current will slightly increase in master mode. DS700PP1 Power Ctl. Registers 02h 03h 1.8 2 1.8 2.5 2.5 2 1.8 2 1.8 2.5 2.5 2 1.8 2.5 CS53L21 Typical Current (mA Total VA VD (Note 20) Power ( 0.01 ...

Page 20

... Architecture The CS53L21 is a highly integrated, low power, 24-bit audio A/D. The ADC operates at 64Fs, where Fs is equal to the system sample rate. The different clock rates maximize power savings while maintaining high performance. The A/D operates in one of four sample rate speed modes: Quarter, Half, Single and Double ...

Page 21

... AIN1A to PGAA AIN1B to PGAB Disabled Invert Enabled Soft Ramp Enabled Zero Cross Disabled MIX ADC Data to SPE ADCA = L; ADCB = R ADC Table 2. Hardware Mode Feature Summary CS53L21 “Recommended Power- Table 2 shows a list of func- Stand-Alone Control Note - - - - - - see Section “MCLKDIV2” pin 2 4.5 on page 29 see Section “ ...

Page 22

... ADCB_ATT[7:0] 0/-96dB 1dB steps TO SIGNAL PROCESSING ENGINE (SPE) FROM SIGNAL PROCESSING ENGINE (SPE) Figure 7. Analog Input Architecture “Analog Characteristics (Commercial - CNZ)” on page 12 for the specified offset level). 55, CS53L21 PGAA_VOL[5:0] ADC_SNGVOL SOFTA PDN_ADCA ZCROSSA +12/-3dB 0.5dB steps AIN1A Multibit AIN2A MUX ...

Page 23

... An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits. DS700PP1 45. 43. Figure 8. Figure CS53L21 51, “Inter- 9. The two channels 23 ...

Page 24

... Figure 8. MIC Input Mix w/Common Mode Rejection 2.15 V 0.35 V 2. ---------------------------------------------- - = 3. μ 2π 50 kΩ 43, “MIC Control (Address 05h)” on page MICIN1 + 17 Σ MICIN2 + 18 1.25 V 1.25 V Full-Scale Differential Input Level (MICMIX=1) = (AINxA - AINxB RMS Figure 9. Differential Input CS53L21 44. MICBIAS 20 2 AINxA AINxB DS700PP1 ...

Page 25

... PGAX Control: ALCA, PGAA (Address 0Ah) & ALCB, PGAB (Address 0Bh)” on Controls: page 49, “MIC Control (Address 05h)” on page DS700PP1 for the input resistance of each path. 40, “MIC Control (Address 05h)” on page 44 “ADCx 47. 40, “ADCx Input Select, Invert & Mute (Address 07h)” on 44. CS53L21 25 ...

Page 26

... ALC) MIN[2:0] below full scale 26 53, MAX[2:0] below full scale RRATE[5:0] ARATE[5:0] Figure 10. ALC CS53L21 52, “ALC Release Rate (Address 1Dh)” on “ALCX & PGAX Control: ALCA, PGAA 49. ADCx_ATT[7:0] and PGAx_VOL[4:0] volume controls should NOT be adjusted manually when ALCx is enabled. MAX[2:0] ...

Page 27

... NG_ALL bit to trigger the noise gate only when both inputs fall below the threshold. Software “Noise Gate Configuration & Misc. (Address 1Fh)” on page Controls: page 45. DS700PP1 “Differential Inputs” on page 23“Differential Inputs” on Output (dB) -52 dB -64 dB -80 dB -96 -40 THRESH[2:0] Figure 11. Noise Gate Attenuation CS53L21 54, “ADC Control (Address 06h)” on Input (dB) 27 ...

Page 28

... MONO signal from a stereo source. The mixer may also be used to imple- ment a left/right channel swap. Software “Channel Mixer (Address 18h)” on page Controls: 28 SIGNAL PROCESSING ENGINE (SPE) MUTE_ADCMIXA MUTE_ADCMIXB ADCMIXA_VOL[6:0] ADCMIXB_VOL[6:0] +12dB/-51.5dB 0.5dB steps VOL Channel ADCA[1:0] Swap ADCB[1:0] Digital Mix to ADC Serial Interface Figure 12. Signal Processing Engine 51. CS53L21 DS700PP1 ...

Page 29

... DS700PP1 “MIC Power Control & Speed Control (Address 03h)” on page (Address 09h)” on page 48. Pin 47 kΩ Pull-down “SDOUT, M/S” pin 29 47 kΩ Pull-up “MCLKDIV2” pin 2 CS53L21 41, “SPE Control Setting Selection Slave Master LO No Divide MCLK is divided by 2 prior HI to all internal circuitry ...

Page 30

... Speed MCLKDIV2 Single ÷ 2 Speed Half ÷ 4 Speed Quarter ÷ 8 Speed Figure 13. Master Mode Timing CS53L21 SSM DSM 128, 192, 256, 384, 128, 192, 256, 384 512, 768 256, 384, 512*, 768* 128, 192, 256*, 384 LRCK Output (Equal to Fs) 10 ...

Page 31

... AOUTA / AINxA DS700PP1 Transmitting Device #2 SDOUT 3ST_SP SCLK/LRCK Receiving Device Figure 14. Tri-State Serial Port “Switching Specifications - Serial Port” on page 14 43. Setting LO Left-Justified Interface HI I²S Interface AOUTB / AINxB Figure 15. I²S Format CS53L21 Figures 15-16 illustrate for exact Selection MSB ...

Page 32

... Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues Figure 16. Left-Justified Format 34 valid write sequence to the control port is not made within approximately Section CS53L21 MSB AOUTB / AINxB Figure 17 on page 33. The A/D enters a 4.5. ...

Page 33

... LRCK valid. desired settings. 2. SCLK valid. 3. Audio samples processed. No RESET = Low Normal Operation Audio signal generated per control port or stand- Figure 17. Initialization Flow Chart CS53L21 Standby Mode Yes 1. No audio signal generated. PDN bit = '1'b? 2. Control Port Registers retain settings Valid ...

Page 34

... All other transitions of SDA occur while the clock is low. The first byte sent to the CS53L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a CS53L21, the chip address field, which is the first byte sent to the CS53L21, should match 100101 fol- lowed by the setting of the AD0 pin ...

Page 35

... MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the CS53L21 after each input byte is read and is input to the CS53L21 from the microcontroller after each transmitted byte SCL CHIP ADDRESS (WRITE) ...

Page 36

... The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. 36 CS53L21 DS700PP1 ...

Page 37

... SPE_ FREEZE Reserved Reserved PGAA DIS VOL4 Reserved PGAB DIS VOL4 ADCA_ ADCA_ ADCA_ ATT6 ATT5 ATT4 ADCB_ ADCB_ ADCB_ ATT6 ATT5 ATT4 CS53L21 Chip_ID0 Rev_ID2 Rev_ID1 PDN_ADCB PDN_ADCA PDN_MICA PDN_ MICBIAS Reserved ADC_I²S/LJ DIGMIX MICBIAS_ MICB_ LVL1 LVL0 BOOST ...

Page 38

... Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ALC_ARATE AALC_RATE ALC_ARATE CS53L21 ADCMIXA ADCMIXA VOL3 VOL2 VOL1 ADCMIXB ADCMIXB VOL3 VOL2 VOL1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ...

Page 39

... SP_CLK default 21h Reserved Reserved Reserved 0 default DS700PP1 ALC_RRATE ALC_RRATE ALC_RRATE MAX1 MAX0 MIN2 NG_BOOST THRESH2 THRESH1 SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL ADCA_OVFL ADCB_OVFL ERR Reserved Reserved Reserved CS53L21 ALC_RRATE ALC_RRATE ALC_RRATE MIN1 MIN0 Reserved Reserved THRESH0 NGDELAY1 NGDELAY0 Reserved Reserved Reserved ...

Page 40

... Chip_ID2 Chip I.D. (Chip_ID[4:0]) Default: 11011 Function: I.D. code for the CS53L21. Permanently set to 11011. Chip Revision (Rev_ID[2:0]) Default: 001 Function: CS53L21 revision level. Revision B is coded as 001. Revision A is coded as 000. 6.2 Power Control 1 (Address 02h Reserved Reserved Reserved Notes: 1 ...

Page 41

... Enables the auto-detect circuitry for detecting the speed mode of the A/D when operating as a slave. When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio. DS700PP1 for the required settings 3-ST_SP PDN_MICB CS53L21 Power Control 1 on page PDN_MICA PDN_MICBIAS MCLKDIV2 Table 3 on page 30. The ...

Page 42

... Function: When enabled, the microphone bias circuit will power-down state. MCLK Divide By 2 (MCLKDIV2) Default Disabled 1 - Divide by 2 Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in Slave Mode. 42 above). CS53L21 DS700PP1 ...

Page 43

... Interface Control (Address 04h Reserved M/S Reserved Master/Slave Mode (M/S) Default Slave 1 - Master Function: Selects either master or slave operation for the serial port. DS700PP1 Reserved Reserved CS53L21 ADC_I²S/LJ DIGMIX MICMIX 43 ...

Page 44

... The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL bit is enabled and the ALC_ENB control register is ignored. 44 “Digital Interface Formats” on page Mix Selected ADC data to ADC serial port, SDOUT data. Reserved SPE Processed ADC data to ADC serial port, SDOUT data CS53L21 31 MICB_BOOST MICA_BOOST DS700PP1 ...

Page 45

... When this bit is set, the internal high-pass filter will be enabled for ADCx. When set to ‘0’, the high-pass filter will be disabled. For DC measurements, this bit must be cleared to ‘0’. on page 14. DS700PP1 SOFTB CS53L21 ZCROSSB SOFTA ZCROSSA “ADC Digital Filter Characteristics” 45 ...

Page 46

... Analog PGA Volume (PGAx_VOL[4:0]) Volume changes immediately. Volume changes at next zero cross time. Volume changes in 0.5 dB steps. Volume changes in 0.5 dB steps at every signal zero-cross. CS53L21 14. Digital Attenuator (ADCx_ATT[7:0]) Volume changes immediately. Volume changes immediately. Change volume in 0.125 dB steps. Change volume in 0.125 dB steps. ...

Page 47

... INV_ADCB Selected Path to ADC AIN1x-->PGAx AIN2x-->PGAx AIN3x/MICINx-->PGAx AIN3x/MICINx-->Pre-Amp (+16/+32 dB Gain) AIN1x AIN2x AIN3x/MICINx Reserved Figure 21. MUX PGA +16 Decoder AINx_MUX[1:0] PDN_PGAx Figure 21. AIN & PGA Selection CS53L21 2 1 INV_ADCA ADCB_MUTE ADCA_MUTE -->PGAx AIN1x AIN2x ADC MUX AIN3x 0 47 ...

Page 48

... FREEZE is disabled. To have multiple changes in the con- trol port registers take effect simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit Reserved Reserved CS53L21 Reserved SPE_SZC1 SPE_SZC0 DS700PP1 ...

Page 49

... Function: Overrides the SOFTx bit setting for the ADC. When this bit is set, the ALC attack rate in the PGA will not be dictated by the soft ramp setting. ALC volume-level changes will take effect in one step. DS700PP1 PGAX_VOL4 PGAX_VOL3 CS53L21 PGAX_VOL2 PGAX_VOL1 PGAX_VOL0 49 ...

Page 50

... Volume Setting +12 dB ··· ··· -0 ··· ADCx_ATT4 ADCx_ATT3 Volume Setting 0 dB ··· ··· -96 dB ··· -96 dB CS53L21 ADCx_ATT2 ADCx_ATT1 ADCx_ATT0 DS700PP1 ...

Page 51

... Reserved Note: The SPE_ENABLE bits in reg09h must be set enable function control in this register. Channel Mixer (ADCx[1:0]) Default: 00 ADCA[1:0] SDOUT 00 L DS700PP1 Volume Setting +12.0 dB ··· -0.5 dB -1.0 dB ··· -51 Reserved ADCA1 ADCB[1:0] SDOUT 00 R CS53L21 ADCA0 ADCB1 ADCB0 51 ...

Page 52

... ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0 ALC Release Rate (RRATE[5:0]) Default: 111111 Binary Code 000000 ··· 111111 52 ADCB[1:0] SDOUT ----------- - Attack Time Fastest Attack ··· Slowest Attack Release Time Fastest Release ··· Slowest Release CS53L21 DS700PP1 ...

Page 53

... The ALC uses this minimum as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the minimum setting. This provides a more natural sound as the ALC attacks and releases. DS700PP1 MIN2 MIN1 CS53L21 MIN0 Reserved Reserved 53 ...

Page 54

... Sets the delay time before the noise gate attacks. Noise gate attenuation is dictated by the SOFTx & ZCROSS bit settings unless the disable bit for each function is enabled THRESH2 THRESH1 Minimum Setting (NG_BOOST = ‘1’b) -64 dB -34 dB -67 dB -37 dB -70 dB -40 dB -73 dB -43 dB -76 dB -46 dB -82 dB -52 dB Reserved -58 dB Reserved -64 dB CS53L21 THRESH0 NGDELAY1 NGDELAY0 DS700PP1 ...

Page 55

... Note: On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes. ADC Overflow (ADCX_OVFL) Default = 0 Function: Indicates that there is an over-range condition anywhere in the CS53L21 ADC signal path of each of the associated ADC’s. DS700PP1 ...

Page 56

... CDB53L21 using an Audio Precision analyzer. -60 -64 -68 - -84 -88 -92 -96 -100 20 50 100 200 Figure 22. ADC THD+N vs. Frequency w/Capacitor Effects 56 shows the THD+N versus frequency for the ADC analog input. Plots were tak- 500 10k 20k Hz CS53L21 1 µF 10 µF 22 µF Legend – Capacitor Value on ADC_FILT+ DS700PP1 ...

Page 57

... MCLK (MHz) 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 MCLK (MHz) 128x 192x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 CS53L21 2048x* 3072x* 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 1024x* 1536x* 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 512x* 768x* 16.3840 24 ...

Page 58

... MCLK (MHz) 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 MCLK (MHz) 128x 192x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 CS53L21 2048x 3072x 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 1024x 1536x 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 512x 768x 16.3840 24 ...

Page 59

... QFN Thermal Pad The CS53L21 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers ...

Page 60

... FILTERS Figure 23. ADC Passband Ripple Figure 25. ADC Transition Band 60 Figure 24. ADC Stopband Rejection Figure 26. ADC Transition Band Detail CS53L21 DS700PP1 ...

Page 61

... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS700PP1 CS53L21 61 ...

Page 62

... JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol 2 Layer Board 4 Layer Board CS53L21 b e Pin #1 Corner L D2 Bottom View MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.23 0.28 5.00 BSC 3.30 3.35 5.00 BSC 3 ...

Page 63

... Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com DS700PP1 Package Pb-Free Grade Temp Range Commercial -10 to +70° C 32L-QFN Yes Automotive -40 to +85° CS53L21 Container Order # Rail CS53L21-CNZ Tape & Reel CS53L21-CNZR Rail CS53L21-DNZ Tape & Reel CS53L21-DNZR - - CDB53L21 63 ...

Page 64

... V IH “Automatic Level Control (ALC)” on page “SPE Control (Address 09h)” on page 26 on page “MIC Control (Address 05h)” on page CS53L21 11. “Analog Characteristics 14. 14. from table in section “” on page 15. ...

Page 65

... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS700PP1 www.cirrus.com. CS53L21 65 ...

Page 66

... CS53L21 DS700PP1 ...

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