CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 44

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

44
6.5
ADC_SNGVOL
7
ADC I²S or Left-Justified (ADC_I²S/LJ)
Default: 0
0 - Left-Justified
1 - I²S
Function:
Selects either the I²S or Left-Justified digital interface format for the data on SDOUT. The required relation-
ship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are detailed in this section
Digital Mix (DIGMIX)
Default: 0
Function:
Routes the ADC outputs to the serial port SDOUT pin. DIGMIX selects either “raw” ADC data or SPE pro-
cessed ADC data to SDOUT. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional.
Microphone Mix (MICMIX)
Default: 0
0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT.
1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT.
Function:
Selects between the ADC stereo mix or a differential mix of analog inputs A and B.
MIC Control (Address 05h)
ADC Single Volume Control (ADC_SNGVOL)
Default: 0
0 - Disabled
1 - Enabled
Function:
The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as
the ALC A and B enable (ALC_ENx) are independently controlled by their respective control registers when
this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator
Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are
ignored. The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL
bit is enabled and the ALC_ENB control register is ignored.
DIGMIX
0
1
ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0
6
SPE_ENABLE
x
0
1
5
ADC data to ADC serial port, SDOUT data.
Reserved
SPE Processed ADC data to ADC serial port, SDOUT data.
“Digital Interface Formats” on page
4
3
Mix Selected
2
31.
MICB_BOOST MICA_BOOST
1
CS53L21
DS700PP1
0