CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 40

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

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6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are
read only. See the following bit definition tables for bit assignment information. The default state of each bit after a
power-up sequence or reset is listed in each bit description.
All “Reserved” registers must maintain their default state.
6.1
6.2
Notes:
Reserved
Chip_ID4
7
7
Chip I.D. and Revision Register (Address 01h) (Read Only)
Chip I.D. (Chip_ID[4:0])
Default: 11011
Function:
I.D. code for the CS53L21. Permanently set to 11011.
Chip Revision (Rev_ID[2:0])
Default: 001
Function:
CS53L21 revision level. Revision B is coded as 001. Revision A is coded as 000.
Power Control 1 (Address 02h)
1. To activate the power-down sequence for individual channels (A or B,) both channels must first be pow-
2. Reserved bits 5 and 6 should always be set “high” by the user to minimize power consumption during
Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the se-
lect channels, 3.) disable the PDN bit.
ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En-
abling the power-down bit on an individual channel basis after the A/D has fully powered up will mute
the selected channel without achieving any power savings.
normal operation.
Reserved
Chip_ID3
6
6
Reserved
Chip_ID2
5
5
PDN_PGAB
Chip_ID1
4
4
PDN_PGAA
Chip_ID0
3
3
PDN_ADCB
Rev_ID2
2
2
PDN_ADCA
Rev_ID1
1
1
CS53L21
DS700PP1
Rev_ID0
PDN
0
0