CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 59

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

DS700PP1
9. PCB LAYOUT CONSIDERATIONS
9.1
9.2
Power Supply, Grounding
As with any high-resolution converter, the CS53L21 requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized.
power arrangements, with VA connected to a clean supply. VD, which powers the digital circuitry, may be
run from the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite
bead. In this case, no additional devices should be powered from VD.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS53L21 as pos-
sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same
side of the board as the CS53L21 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+ and VQ pins in order to avoid unwanted coupling into the modulators. The FILT+
and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the electrical path
from FILT+ and AGND. The CS53L21 evaluation board demonstrates the optimum layout and power supply
arrangements.
QFN Thermal Pad
The CS53L21 is available in a compact QFN package. The under side of the QFN package reveals a large
metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with
an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of
vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-
mance. The CS53L21 evaluation board demonstrates the optimum thermal pad and via configuration.
Figure 1 on page 9
shows the recommended
CS53L21
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