CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 31

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

DS700PP1
4.5.3
4.5.4
4.6
LRCK
SCLK
SDIN
Digital Interface Formats
The serial port operates in standard I²S or Left-Justified digital interface formats with varying bit depths from
16 to 24. Data is clocked out of the ADC or into the SPE on the rising edge of SCLK.
the general structure of each format. Refer to
timing relationship between clocks and data.
Hardware
High-Impedance Digital Output
The serial port may be placed on a clock/data bus that allows multiple masters for the serial port I/O with-
out the need for external buffers. The 3ST_SP bit places the internal buffers for these I/O in a high-imped-
ance state, allowing another device to transmit serial port data without bus contention..
Quarter- and Half-Speed Mode
Quarter-Speed Mode (QSM) and Half-Speed Mode (HSM) allow lower sample rates while maintaining a
relatively flat noise floor in the typical audio band of 20 Hz - 20 kHz. Single-Speed Mode (SSM) will allow
lower frequency sample rates.
Software
Control:
Control:
M S B
“Interface Control (Address 04h)” on page
Transmitting Device #1
AOUTA / AINxA
“I²S/LJ” pin 3
L eft C h a n n e l
Pin
CS53L21
3ST_SP
Figure 14. Tri-State Serial Port
Setting
Figure 15. I²S Format
L S B
LO
HI
Receiving Device
SCLK/LRCK
“Switching Specifications - Serial Port” on page 14
SDOUT
Left-Justified Interface
I²S Interface
43.
M S B
Transmitting Device #2
AOUTB / AINxB
R ig ht C h a n n e l
Selection
Figures 15-16
L S B
CS53L21
for exact
illustrate
MSB
31