CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 34

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

34
4.10
4.10.1 SPI Control
4.10.2 I²C Control
Software Mode
The control port is used to access the registers allowing the A/D to be configured for the desired operational
modes and formats. The operation of the control port may be completely asynchronous with respect to the
audio sample rates. However, to avoid potential interference problems, the control port pins should remain
static if no operation is required.
The control port operates in two modes: SPI and I²C, with the A/D acting as a slave device. Software Mode
is selected if there is a high-to-low transition on the AD0/CS pin after the RESET pin has been brought high.
I²C Mode is selected by connecting the AD0/CS pin through a resistor to VL or DGND, thereby permanently
selecting the desired AD0 bit address state.
In Software Mode, CS is the CS53L21 chip-select signal, CCLK is the control port bit clock (input into the
CS53L21 from the microcontroller), CDIN is the input data line from the microcontroller. Data is clocked
in on the rising edge of CCLK. The A/D will only support write operations. Read request will be ignored.
Figure 18
The first seven bits on CDIN form the chip address and must be 1001010. The eighth bit is a read/write
indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP.
There is MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment
after each byte is read or written, allowing block reads or writes of successive registers.
In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pin AD0 forms the least significant bit of the chip address and should be connected
through a resistor to VL or DGND as desired. The state of the pin is sensed while the CS53L21 is being
reset.
The signal timings for a read and write cycle are shown in
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS53L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a
CS53L21, the chip address field, which is the first byte sent to the CS53L21, should match 100101 fol-
lowed by the setting of the AD0 pin. The eighth bit of the address is the R/W bit. If the operation is a write,
the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the
operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-
CCLK
CDIN
CS
shows the operation of the control port in Software Mode. To write to a register, bring CS low.
0
1
CHIP ADDRESS (WRITE)
1
0
2
0
3
1
4
0
Figure 18. Control Port Timing in SPI Mode
5
1
6
0
7
0
INCR
8
9
6
10 11
MAP BYTE
5
4
12
3
13 14 15
2
1
0
16 17
7
6
DATA
Figure 19
1
0
7
and
DATA +n
6
Figure
1
0
20. A Start condition is
CS53L21
DS700PP1