CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 30

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

30
4.5.1
4.5.2
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on
the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then
require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone
control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the A/D operates in single-speed only. In Software Mode, the A/D operates in either
quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
*MCLKDIV2 must be enabled.
Auto-Detect
Mode only)
(Software
Disabled
Enabled
MCLK
512, 768, 1024, 1536,
1024, 1536, 2048*,
2048, 3072
QSM
3072*
÷ 1
÷ 2
Figure 13. Master Mode Timing
MCLKDIV2
0
1
512, 768, 1024*, 1536*
Table 3. MCLK/LRCK Ratios
256, 384, 512, 768,
1024, 1536
HSM
÷ 128
÷ 128
÷ 256
÷ 512
÷ 2
÷ 2
÷ 4
÷ 8
Double
Speed
Quarter
Quarter
Single
Speed
Speed
Speed
Double
Single
Speed
Speed
Speed
Speed
Half
Half
256, 384, 512*, 768*
128, 192, 256, 384,
SPEED[1:0]
00
01
10
11
00
01
10
11
512, 768
SSM
LRCK Output
SCLK Output
(Equal to Fs)
128, 192, 256*, 384*
128, 192, 256, 384
DSM
CS53L21
DS700PP1