CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 26

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

26
4.3.7
Automatic Level Control (ALC)
When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak
levels exceed the maximum threshold settings and lowers, first, the PGA gain settings and then increases
the digital attenuation levels at a programmable attack rate and maintains the resulting level below the
maximum threshold.
When input signal levels fall below the minimum threshold, digital attenuation levels are decreased first
and the PGA gain is then increased at a programmable release rate and maintains the resulting level
above the minimum threshold.
Attack and release rates are affected by the ADC soft ramp/zero cross settings and sample rate, Fs. ALC
soft ramp and zero cross dependency may be independently enabled/disabled.
Recommended settings: Best level control may be realized with the fastest attack and slowest release
setting with soft ramp enabled in the control registers. Note: 1.) The maximum realized gain must be set
in the PGAx_VOL register. The ALC will only apply the gain set in the PGAx_VOL. 2.) The ALC maintains
the output signal between the MIN and MAX thresholds. As the input signal level changes, the level-con-
trolled output may not always be the same but will always fall within the thresholds.
Software
Controls:
below full scale
below full scale
MIN[2:0]
MIN[2:0]
(after ALC)
Output
ALC
Input
PGA Gain and/or
Attenuator
“ALC Enable & Attack Rate (Address 1Ch)” on page
page
(Address 0Ah) & ALCB, PGAB (Address 0Bh)” on page
52,
“ALC Threshold (Address 1Eh)” on page
RRATE[5:0]
Figure 10. ALC
ARATE[5:0]
MAX[2:0]
below full scale
53,
MAX[2:0]
below full scale
52,
adjusted manually when
PGAx_VOL[4:0] volume
controls should NOT be
“ALCX & PGAX Control: ALCA, PGAA
ADCx_ATT[7:0] and
49.
“ALC Release Rate (Address 1Dh)” on
ALCx is enabled.
CS53L21
DS700PP1