CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 35

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

DS700PP1
SCL
SDA
SDA
SCL
START
increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated
by an acknowledge bit. The ACK bit is output from the CS53L21 after each input byte is read and is input
to the CS53L21 from the microcontroller after each transmitted byte.
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
START
Figure
0
1
CHIP ADDRESS (WRITE)
0
1
1
0
CHIP ADDRESS (WRITE)
Send start condition.
Send 100101x0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto-increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 100101x1 (chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
0
2
1
0
20, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
1
3
0
2
0 1 AD0 0
4
1
3
5
0
4
6
1
5
7
AD0
ACK
6
8
7
9
INCR
0
ACK
10 11
Figure 20. Control Port Timing, I²C Read
Figure 19. Control Port Timing, I²C Write
8
6
INCR
9
5
MAP BYTE
12 13 14 15
10 11
4
6
MAP BYTE
3
5
2
12
4
1
13 14 15
3
16
0
ACK
2
STOP
17 18
START
1
16 17 18
0
19
ACK
1
20 21 22 23 24
CHIP ADDRESS (READ)
0
7
0
19
6
DATA
1
0
24 25
1
1 AD0 1
0
25
ACK
26
26 27 28
27 28
ACK
7
DATA +1
6
7
DATA
0
1
ACK
0
DATA +1
7
7
DATA +n
0
6
DATA + n
1
7
CS53L21
0
0
ACK
ACK
NO
STOP
STOP
35