CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 21

IC ADC STEREO 24BIT 98DB 32QFN

CS53L21-CNZ

Manufacturer Part Number
CS53L21-CNZ
Description
IC ADC STEREO 24BIT 98DB 32QFN
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS53L21-CNZ

Package / Case
32-QFN
Number Of Converters
2
Number Of Bits
24
Sampling Rate (per Second)
100k
Data Interface
Serial
Power Dissipation (max)
30mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
96 KSPS
Resolution
24 bit
Number Of Adc Inputs
6
Operating Supply Voltage
1.8 V or 2.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 10 C
Mounting Style
SMD/SMT
Power Consumption
60 mW
Supply Voltage (max)
2.63 V
Supply Voltage (min)
1.65 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1550 - BOARD EVAL FOR CS53L21 ADC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1191

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS53L21-CNZR
Manufacturer:
CIRRUS
Quantity:
20 000
DS700PP1
4.2
Power Control
Auto-Detect
Speed Mode
MCLK Divide
Serial Port Master / Slave Selection
Interface Control
ADC Volume & Gain
ADCx High-Pass Filter
ADCx High-Pass Filter Freeze
Line/MIC Input Select
ADC mix Volume and Gain
Signal Processing Engine (SPE)
Data Selection (SPE Enable)
Channel Swap
Hardware Mode
A limited feature-set is available when the A/D powers up in Hardware Mode (see
Up Sequence” on page
tions/features, the default configuration and the associated stand-alone control available.
Feature/Function
MICx Pre-Amplifier
Serial Port Master
Serial Port Slave
32) and may be controlled via stand-alone control pins.
Digital Boost
Hardware Mode Feature/Function Summary
Noise Gate
Zero Cross
Zero Cross
Soft Ramp
Soft Ramp
Attenuator
MIC Bias
Table 2. Hardware Mode Feature Summary
Device
PGAx
ADCx
PGAx
Invert
Invert
ADC
ADC
ALC
MIX
Continuous DC Subtraction
Default Configuration
Auto-Detect Speed Mode
ADCA = L; ADCB = R
Single-Speed Mode
ADC Data to SPE
AIN1A to PGAA
AIN1B to PGAB
Powered Down
Powered Down
Powered Up
Powered Up
Powered Up
(Selectable)
(Selectable)
(Selectable)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
0 dB
0 dB
Stand-Alone Control
“MCLKDIV2” pin 2
“I²S/LJ” pin 3
“M/S” pin 29
Table 2
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“Recommended Power-
shows a list of func-
CS53L21
4.5 on page 29
4.5 on page 29
4.6 on page 31
see Section
see Section
see Section
Note
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21

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