CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 33

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

DS700PP1
4.9
1. Audible pops.
Power Off Transition
Recommended Power-Down Sequence
To minimize audible pops when turning off or placing the A/D in standby,
1. Mute the ADC’s.
2. Set the PDN bit in the power control register to ‘1’b. The A/D will not power down until it reaches a fully
3. Bring RESET low.
1. Pops suppressed.
muted sate. Do not remove MCLK until after the part has fully muted. Note that it may be necessary to
disable the soft ramp and/or zero cross volume transitions to achieve faster muting/power down.
Reset Transition
ERROR: Power removed
Hardware Mode
Minimal feature
set support.
1. No audio signal generated.
2. Control Port Registers reset
to default.
No
Off Mode (Power Applied)
1. No audio signal
generated.
Control Port Valid
Write Seq. within
RESET = Low?
Control Port
No Power
10 ms?
Active
No
Registers setup to
desired settings.
Software Mode
Figure 17. Initialization Flow Chart
Yes
Yes
RESET = Low
Audio signal generated per control port or stand-
No
1. LRCK valid.
2. SCLK valid.
3. Audio samples
processed.
Sub-Clocks Applied
ADC Initialization
Normal Operation
1. VQ Charged to
quiescent voltage.
2. Filtx+ Charged.
MCLK cycle delay
MCLK Applied?
PDN bit = '1'b?
alone settings.
Charge Caps
2048 internal
MCLK/LRCK
20 ms delay
Ratio?
Valid
Valid
Yes
No
Yes
No
PDN bit set to '1'b
(software mode only)
1. No audio signal generated.
2. Control Port Registers retain
settings.
CS53L21
Standby Mode
33