CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 52

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

52
6.13
6.14
ALC_ENB
Reserved
7
7
Function:
Implements mono mixes of the left and right channels as well as a left/right channel swap.
ALC Enable & Attack Rate (Address 1Ch)
ALC Enable (ALC_ENX)
Default: 0
0 - Disabled
1 - Enabled
Function:
Enables automatic level control for ADC channel x.
Note:
ALC Attack Rate (ARATE[5:0])
Default: 000000
Function:
Sets the rate at which the ALC attenuates the analog input from levels above the maximum setting in the
ALC threshold register.
The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and the SOFTx
& ZCROSSx bit settings unless the disable bit for each function is enabled.
ALC Release Rate (Address 1Dh)
ALC Release Rate (RRATE[5:0])
Default: 111111
ADCA[1:0]
Binary Code
Binary Code
000000
000000
01
10
11
111111
111111
ALC_ENA
When the ALC is enabled, the Attenuator and PGA volume is automatically controlled and should
not be adjusted manually.
Reserved
···
···
6
6
SDOUT
L
----------- -
ALC_RRATE5 ALC_RRATE4 ALC_RRATE3 ALC_RRATE2 ALC_RRATE1 ALC_RRATE0
ALC_ARATE5 ALC_ARATE4 ALC_ARATE3 ALC_ARATE2 ALC_ARATE1 ALC_ARATE0
+
2
R
R
5
5
Slowest Release
Fastest Release
Release Time
Slowest Attack
Attack Time
Fastest Attack
ADCB[1:0]
···
···
01
10
11
4
4
SDOUT
L
----------- -
+
2
L
R
3
3
2
2
1
1
CS53L21
DS700PP1
0
0