CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 22

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

22
4.3
4.3.1
DIGMIX
MUX
MUX
AINxA and AINxB are the analog inputs, internally biased to VQ, that accepts line-level and MIC-level sig-
nals, allowing various gain and signal adjustments for each channel.
Analog Inputs
Digital Code, Offset & DC Measurement
The ADC output data is in two’s complement binary format. For inputs above positive full scale or below
negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC overflow
bit to be set to a ‘1’.
Given the two’s complement format, low-level signals may cause the MSB of the serial data to periodically
toggle between ‘1’ and ‘0’, possibly introducing noise into the system as the bit switches back and forth.
To prevent this phenomena, a constant DC offset is added to the serial data bringing the low-level signal
just above the point at which the MSB would normally toggle, thus reducing the noise introduced. Note
that this offset is not removed (refer to
“Analog Characteristics (Automotive - DNZ)” on page 13
The A/D may be used to measure DC voltages by disabling the high-pass filter for the designated channel.
DC levels are measured relative to VQ and will be decoded as positive two’s complement binary numbers
above VQ and negative two’s complement binary numbers below VQ.
Software
Controls:
MICMIX
MUX
MUX
“Status (Address 20h) (Read Only)” on page
Σ
ADCA_HPF FREEZE
ADCA_HPF ENABLE
ADCB_HPF FREEZE
ADCB_HPF ENABLE
ALC_ARATE[5:0]
ALC_RRATE[5:0]
ALCA_SRDIS
ALCA_ZCDIS
ALCB_SRDIS
ALCB_ZCDIS
MAX[2:0]
MIN[2:0]
ALC_ENB
ALC_ENA
Figure 7. Analog Input Architecture
ADCA_DBOOST
ALC
TO SIGNAL PROCESSING
ENGINE (SPE)
FROM SIGNAL
PROCESSING ENGINE
(SPE)
ADCB_DBOOST
+20dB
+20dB
Digital
Digital
Boost
Boost
“Analog Characteristics (Commercial - CNZ)” on page 12
ADCA_ATT[7:0]
ADCB_ATT[7:0]
ADCB_MUTE
1dB steps
0/-96dB
SOFTB
ADCA_MUTE
1dB steps
SOFTA
0/-96dB
Attenuator
Attenuator
Noise Gate
55,
for the specified offset level).
PDN_ADCA
“ADC Control (Address 06h)” on page
PDN_ADCB
NG_ALL
NG_EN
THRESH[3:0]
NGDELAY[1:0]
Oversampling
Oversampling
INV_ADCA
INV_ADCB
Multibit
Multibit
ADC
ADC
PGA
PGA
PDN_PGAB
AINB_MUX[1:0]
AINA_MUX[1:0]
PGAA_VOL[5:0]
ADC_SNGVOL
SOFTA
ZCROSSA
MICBIAS_LVL[1:0]
PDN_MICBIAS
0.5dB steps
0.5dB steps
PGAB_VOL[5:0]
ADC_SNGVOL
SOFTB
ZCROSSB
PDN_PGAA
+12/-3dB
+12/-3dB
MUX
MUX
MICBIAS
32 dB
+16/
32 dB
+16/
MICBIAS_SEL
PDN_MICA
MICA_BOOST
PDN_MICB
MICB_BOOST
CS53L21
DS700PP1
AIN1A
AIN2A
AIN3A/ MICIN1
AIN1B
AIN2B/MICBIAS
AIN3B/ MICIN2/
MICBIAS
45.
and/or