CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 41

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

CS53L21
Power Down PGA X (PDN_PGAX)
Default: 0
0 - Disable
1 - Enable
Function:
PGA channel x will either enter a power-down or muted state when this bit is enabled. See
Power Control
1 (Address 02h) Note 1
above.
This bit is used in conjunction with AINx_MUX bits to determine the analog input path to the ADC. Refer to
“ADCX Input Select Bits (AINX_MUX[1:0])” on page 47
for the required settings.
Power Down ADC X (PDN_ADCX)
Default: 0
0 - Disable
1 - Enable
Function:
ADC channel x will either enter a power-down or muted state when this bit is enabled. See Note
1 on page
40.
Power Down (PDN)
Default: 0
0 - Disable
1 - Enable
Function:
The entire A/D will enter a low-power state when this function is enabled. The contents of the control port
registers are retained in this mode.
6.3
MIC Power Control & Speed Control (Address 03h)
7
6
5
4
3
2
1
0
AUTO
SPEED1
SPEED0
3-ST_SP
PDN_MICB
PDN_MICA PDN_MICBIAS
MCLKDIV2
Auto-Detect Speed Mode (AUTO)
Default: 1
0 - Disable
1 - Enable
Function:
Enables the auto-detect circuitry for detecting the speed mode of the A/D when operating as a slave. When
AUTO is enabled, the MCLK/LRCK ratio must be implemented according to
Table 3 on page
30. The
SPEED[1:0] bits are ignored when this bit is enabled. Speed is determined by the MCLK/LRCK ratio.
DS700PP1
41