CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 23

• Manufacturer Part Number: CS53L21-CNZ
• Description: IC ADC STEREO 24BIT 98DB 32QFN
• Manufacturer: Cirrus Logic Inc

Specifications of CS53L21-CNZ

• Package / Case: 32-QFN
• Number Of Converters: 2
• Number Of Bits: 24
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Power Dissipation (max): 30mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 96 KSPS
• Resolution: 24 bit
• Number Of Adc Inputs: 6
• Operating Supply Voltage: 1.8 V or 2.5 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: - 10 C
• Mounting Style: SMD/SMT
• Power Consumption: 60 mW
• Supply Voltage (max): 2.63 V
• Supply Voltage (min): 1.65 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1550 - BOARD EVAL FOR CS53L21 ADC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1191

DS700PP1
4.3.2
4.3.3
4.3.4
4.3.4.1
The microphone input is internally biased to VQ. Input signals must be AC coupled using external capaci-
tors with values consistent with the desired high-pass filter design. The MICINx input resistance of 50 kW
may be combined with an external capacitor of 1 mF to achieve the cutoff frequency defined by the equa-
tion,
An electrolytic capacitor must be placed such that the positive terminal is positioned relative to the side with
the greater bias voltage. The MICBIAS voltage level is controlled by the MICBIAS_LVL[1:0] bits.
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. If the high-pass filter is “frozen” during normal operation, the current value of the DC offset for the
corresponding channel is held. It is this DC offset that will continue to be subtracted from the conversion
result. This feature makes it possible to perform a system DC offset calibration by:
1. Running the A/D with the high-pass filter enabled and the DC offset not “frozen” until the filter settles.
2. Freezing the DC offset.
The high-pass filters are controlled using the ADCx_HPFRZ and ADCx_HPFEN bits.
If a particular ADC channel is used to measure DC voltages, the high-pass filter may be disabled using
the ADCx_HPFEN bit.
Digital Routing
The digital output of the ADC may be internally routed to the Signal Processing Engine (SPE). ADC output
volume may be controlled using the ADCMIX [6:0] bits, and channel swaps can be done using the
ADCA[1:0] and ADCB[1:0] bits. This “processed” ADC data can be selected for output in place of the ADC
output data using the DIGMIX bit.
Differential Inputs
The stereo pair inputs act as a single differential input when the MICMIX bit is enabled. This provides com-
mon mode rejection of noise in digitally intense PCB’s where the microphone signal traverses long traces,
or across long microphone cables as illustrated in
Since the mixer provides a differential combination of the two signals, the potential input mix may exceed
the maximum full-scale input and result in clipping. The level out of the mixer, therefore, is automatically
attenuated 6 dB. Gain may be applied using either the analog PGA or MIC Pre-amp or the digital ADCMIX
volume control to re-adjust a small signal to desired levels.
The analog inputs may also be used as a differential input pair as illustrated in
are differentially combined when the MICMIX bit is enabled.
Software
Controls:
Software
Controls:
See the Digital Filter Characteristics for filter settling time.
External Passive Components
“ADC Control (Address 06h)” on page
“ADCx Mixer Volume Control: ADCA (Address 0Eh) & ADCB (Address 0Fh)” on page
face Control (Address 04h)” on page
43.
45.
Figure
8.
Figure
9. The two channels
CS53L21
51,
“Inter-
23