CS53L21-CNZ Cirrus Logic Inc, CS53L21-CNZ Datasheet - Page 47

IC ADC STEREO 24BIT 98DB 32QFN

CS53L21-CNZ

Manufacturer Part Number
CS53L21-CNZ
Description
IC ADC STEREO 24BIT 98DB 32QFN
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS53L21-CNZ

Package / Case
32-QFN
Number Of Converters
2
Number Of Bits
24
Sampling Rate (per Second)
100k
Data Interface
Serial
Power Dissipation (max)
30mW
Voltage Supply Source
Analog and Digital
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
96 KSPS
Resolution
24 bit
Number Of Adc Inputs
6
Operating Supply Voltage
1.8 V or 2.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
- 10 C
Mounting Style
SMD/SMT
Power Consumption
60 mW
Supply Voltage (max)
2.63 V
Supply Voltage (min)
1.65 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1550 - BOARD EVAL FOR CS53L21 ADC
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1191

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS53L21-CNZR
Manufacturer:
CIRRUS
Quantity:
20 000
DS700PP1
6.7
AINB_MUX1
7
ADCx Input Select, Invert & Mute (Address 07h)
ADCX Input Select Bits (AINX_MUX[1:0])
Default: 00
Function:
Selects the specified analog input signal into ADCx. The microphone pre-amplifier is only available when
PDN_PGAx is disabled. See
ADCX Invert Signal Polarity (INV_ADCX)
Default: 0
0 - Disabled
1 - Enabled
Function:
When enabled, this bit will invert the signal polarity of the ADC x channel.
ADCX Channel Mute (ADCX_MUTE)
Default: 0
0 - Disabled
1 - Enabled
Function:
The output of channel x ADC will mute when enabled. The muting function is affected by the ADCx Soft bit
(SOFT).
PDN_PGAx AINx_MUX[1:0]
0
0
0
0
1
1
1
1
AINB_MUX0
6
AIN3x / MICINx
AINA_MUX1
00
01
10
11
00
01
10
11
AIN1x
AIN2x
5
Figure
AIN1x-->PGAx
AIN2x-->PGAx
AIN3x/MICINx-->PGAx
AIN3x/MICINx-->Pre-Amp
AIN1x
AIN2x
AIN3x/MICINx
Reserved
Figure 21. AIN & PGA Selection
AINA_MUX0
21.
32 dB
+16/
AINx_MUX[1:0]
4
PDN_PGAx
MUX
Selected Path to ADC
INV_ADCB
3
(+16/+32 dB Gain)
Decoder
PGA
AIN1x
AIN2x
AIN3x
INV_ADCA
2
-->PGAx
MUX
ADCB_MUTE ADCA_MUTE
1
ADC
CS53L21
0
47

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