EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet

IC APEX 20KE FPGA 100K 324-FBGA

EP20K100EFC324-2

Manufacturer Part Number
EP20K100EFC324-2
Description
IC APEX 20KE FPGA 100K 324-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet

Specifications of EP20K100EFC324-2

Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
246
Number Of Gates
263000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
246
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Features
Altera Corporation
DS-APEX20K-5.1
Maximum
system
gates
Typical
gates
LEs
ESBs
Maximum
RAM bits
Maximum
macrocells
Maximum
user I/O
pins
March 2004, ver. 5.1
Table 1. APEX 20K Device Features
Feature
EP20K30E
113,000
30,000
24,576
1,200
192
128
12
EP20K60E
162,000
60,000
32,768
2,560
256
196
16
Industry’s first programmable logic device (PLD) incorporating
system-on-a-programmable-chip (SOPC) integration
High density
MultiCore
product-term logic, and embedded memory
LUT logic used for register-intensive functions
Embedded system block (ESB) used to implement memory
functions, including first-in first-out (FIFO) buffers, dual-port
RAM, and content-addressable memory (CAM)
ESB implementation of product-term logic used for
combinatorial-intensive functions
30,000 to 1.5 million typical gates (see
Up to 51,840 logic elements (LEs)
Up to 442,368 RAM bits that can be used without reducing
available logic
Up to 3,456 product-term-based macrocells
Note (1)
EP20K100
263,000
100,000
53,248
4,160
416
252
26
TM
architecture integrating look-up table (LUT) logic,
EP20K100E EP20K160E
263,000
100,000
53,248
4,160
416
246
26
404,000
160,000
81,920
6,400
640
316
40
Programmable Logic
Tables 1
EP20K200
526,000
200,000
106,496
8,320
832
382
52
Device Family
APEX 20K
and 2)
EP20K200E
Data Sheet
526,000
200,000
106,496
8,320
832
376
52
1

Related parts for EP20K100EFC324-2

EP20K100EFC324-2 Summary of contents

Page 1

... Maximum 24,576 RAM bits Maximum 192 macrocells Maximum 128 user I/O pins Altera Corporation DS-APEX20K-5.1 ■ Industry’s first programmable logic device (PLD) incorporating system-on-a-programmable-chip (SOPC) integration – MultiCore TM architecture integrating look-up table (LUT) logic, product-term logic, and embedded memory – ...

Page 2

... Table 3) Table 3) Device EP20K30E EP20K60E EP20K100E EP20K160E EP20K200E EP20K300E EP20K400E EP20K600E EP20K1000E EP20K1500E 1.8 V 1.8 V, 2.5 V, 3.3 V, 5.0 V Altera Corporation 2,392,000 1,500,000 51,840 216 442,368 3,456 808 (1) ...

Page 3

... Available in a variety of packages with 144 to 1,020 pins (see Tables 4 through 7) ® – FineLine BGA packages maximize board space efficiency ■ Advanced software support – Software design support and automatic place-and-route provided by the Altera + 250 MHz CO SU Table 3) CCIO ® Interconnect structure ® ...

Page 4

... EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E 4 Windows-based PCs, Sun SPARCstations, and HP 9000 Series 700/800 workstations ® – Altera MegaCore functions and Altera Megafunction Partners SM Program (AMPP ) megafunctions TM – NativeLink integration with popular synthesis, simulation, and timing analysis tools ® – Quartus II SignalTap ...

Page 5

... FineLine BGA, and pin-grid array (PGA) packages. (3) This device uses a thermally enhanced package, which is taller than the regular package. Consult the Altera Device Package Information Data Sheet for detailed package size information. Table 6. APEX 20K QFP, BGA & PGA Package Sizes ...

Page 6

... APEX 20KE devices extend the APEX 20K family to 1.5 million gates. APEX 20KE devices are denoted with an “E” suffix in the device name (e.g., the EP20K1000E device is an APEX 20KE device). compares the features included in APEX 20K and APEX 20KE devices. Table 8 Altera Corporation ...

Page 7

... PCI 32/64-Bit, 66-MHz PCI MultiVolt I/O ClockLock support Dedicated clock and input pins Six I/O standard support Memory support Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet APEX 20K Devices Full support Full support Full compliance in -1, -2 speed grades - 2 ...

Page 8

... APEX 20K devices can be configured on the board for the specific functionality required. APEX 20K devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable EPC1, EPC2, and EPC16 configuration devices, which configure APEX 20K devices via a serial data stream ...

Page 9

... IOE Product Term state machines. Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet APEX 20K devices incorporate LUT-based logic, product-term-based logic, and memory into one device. Signal interconnections within APEX 20K devices (as well as to and from device pins) are provided by the ® ...

Page 10

... Figure 2 MegaLAB Interconnect LE1 LE1 LE2 LE2 LE3 LE3 LE4 LE4 LE5 LE5 LE6 LE6 LE7 LE7 LE8 LE8 LE9 LE9 LE10 LE10 shows the MegaLAB structure. LE1 LE2 LE3 LE4 LE5 LE6 LE7 LE8 LE9 LE10 LABs Altera Corporation TM ESB ...

Page 11

... To/From Adjacent LAB, ESB, or IOEs Local Interconnect Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Logic Array Block Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains, LAB control signals, and the local interconnect. The local interconnect transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs ...

Page 12

... The LAB-wide control signals can be generated from the LAB local interconnect, global signals, and dedicated clock pins. The inherent low skew of the FastTrack Interconnect enables used for clock distribution. Figure 4 shows the LAB control signal generation circuit (1) 4 SYNCLOAD or LABCLKENA2 SYNCCLR or LABCLK2 (3) LABCLKENA1 LABCLR1 (2) LABCLR2 (2) LABCLK1 Altera Corporation ...

Page 13

... Carry-Out Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Logic Element The LE, the smallest unit of logic in the APEX 20K architecture, is compact and provides efficient logic usage. Each LE contains a four-input LUT, which is a function generator that can quickly implement any function of four variables ...

Page 14

... Another portion of the LUT and the carry chain logic generates the carry-out signal, which is routed directly to the carry- in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is driven onto the local, MegaLAB, or FastTrack Interconnect routing structures. ™ structure. A carry chain longer Altera Corporation ...

Page 15

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 6. APEX 20K Carry Chain Carry-In a1 LUT b1 Carry Chain a2 LUT b2 Carry Chain an LUT bn Carry Chain LUT Carry Chain s1 Register LE1 s2 Register LE2 sn Register LEn Register Carry-Out LEn + 1 15 ...

Page 16

... LE of the third LAB in the MegaLAB structure. shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. OR Cascade Chain LE1 LE2 d[(4 n – 1)..(4 n – 4 d[3..0] LUT d[7..4] LUT LUT Altera Corporation Figure 7 LE1 LE2 LE n ...

Page 17

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet LE Operating Modes The APEX 20K LE can operate in one of the following three modes: ■ Normal mode ■ Arithmetic mode ■ Counter mode Each mode uses LE resources differently. In each mode, seven available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE— ...

Page 18

... Cascade-Out Carry-Out LAB-Wide Synchronous Cascade-In Load (6) 3-Input LUT 3-Input LUT Carry-Out Cascade-Out PRN D Q ENA CLRN LAB-Wide Clock Enable (2) PRN D Q ENA CLRN LAB-Wide Synchronous Clear (6) LAB-Wide Clock Enable (2) PRN D Q ENA CLRN Altera Corporation LE-Out LE-Out LE-Out LE-Out LE-Out LE-Out ...

Page 19

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Normal Mode The normal mode is suitable for general logic applications, combinatorial functions, or wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in are inputs to a four-input LUT ...

Page 20

... The row interconnect routes signals throughout a row of MegaLAB structures; the column interconnect routes signals throughout a column of MegaLAB structures. When using the row and column interconnect, an LE, IOE, or ESB can drive any other LE, IOE, or ESB in a device. See Figure 9. Altera Corporation ...

Page 21

... I/O Interconnect MegaLAB I/O MegaLAB I/O Column Interconnect MegaLAB I/O I/O Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet I/O MegaLAB MegaLAB MegaLAB MegaLAB MegaLAB MegaLAB I/O A row line can be driven directly by LEs, IOEs, or ESBs in that row. Further, a column line can drive a row line, allowing an LE, IOE, or ESB to drive elements in a different row via the column and row interconnect ...

Page 22

... APEX 20K Programmable Logic Device Family Data Sheet Figure 10. FastTrack Connection to Local Interconnect I MegaLAB Column 22 I/O Row MegaLAB MegaLAB Interconnect MegaLAB Interconnect Drives Local Interconnect Row & Column Interconnect Drives MegaLAB Interconnect Row Column Altera Corporation ...

Page 23

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 11 shows the intersection of a row and column interconnect, and how these forms of interconnects and LEs drive each other. Figure 11. Driving the FastTrack Interconnect Row Interconnect MegaLAB Interconnect LE Local Interconnect APEX 20KE devices include an enhanced interconnect structure for faster routing of input signals with high fan-out. Column I/O pins can drive the ™ ...

Page 24

... FastRow Interconnect IOE Drives Local Interconnect in Two MegaLAB Structures MegaLAB Table 9 summarizes how various elements of the APEX 20K architecture drive each other. Select Vertical I/O Pins IOE IOE Drive Local Interconnect and FastRow Interconnect MegaLAB LABs Altera Corporation Local Interconnect LEs ...

Page 25

... Interconnect MegaLAB Interconnect Row FastTrack Interconnect Column FastTrack Interconnect FastRow Interconnect Note to Table 9: (1) This connection is supported in APEX 20KE devices only. Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Destination LE ESB Local Interconnect (1) Product-Term Logic The product-term portion of the MultiCore architecture is implemented with the ESB ...

Page 26

... Quartus II software uses this feature to perform DeMorgan’s inversion for more efficient implementation of wide OR functions. The Quartus II software Compiler can use a NOT-gate push-back technique to emulate an asynchronous preset. Figure 14 MegaLAB Interconnect 9 32 Macrocell Inputs (1-16 CLK[1..0] 2 ENA[1..0] 2 CLRN[1..0] shows the APEX 20K macrocell. Altera Corporation To Row and Column Interconnect ...

Page 27

... Figure 14. APEX 20K Macrocell Product- 32 Signals from Local Interconnect Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet ESB-Wide ESB-Wide Clears Clock Enables 2 Parallel Logic Expanders (From Other Macrocells) Term Select Matrix For registered functions, each macrocell register can be programmed individually to implement operation with programmable clock control ...

Page 28

... ESB. The Quartus II software Compiler can allocate sets two parallel expanders per set to the macrocells automatically. Each set of two parallel expanders incurs a small, incremental timing delay. shows the APEX 20K parallel expanders. CLK1 CLKENA1 CLR2 CLR1 Figure 16 Altera Corporation Figure 15 ...

Page 29

... Figure 16. APEX 20K Parallel Expanders 32 Signals from Local Interconnect Embedded System Block Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet From Previous Macrocell Product- Term Select Matrix Parallel Expander Switch Product- Term Select Matrix Parallel Expander Switch The ESB can implement various types of memory blocks, including dual-port RAM, ROM, FIFO, and CAM blocks. The ESB includes input and output registers ...

Page 30

... ESB driver is turned on, driving the output to the tri-state line. The Quartus II software automatically combines ESBs with tri-state lines to form deeper memory blocks. The internal tri-state control logic is designed to avoid internal contention and floating lines. See Figure 18. Altera Corporation ...

Page 31

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 18. Deep Memory Block Implemented with Multiple ESBs Address Decoder ESB ESB ESB The ESB implements two forms of dual-port memory: read/write clock mode and input/output clock mode. The ESB can also be used for bidirectional, dual-port memory applications in which two ports read or write simultaneously ...

Page 32

... ENA D Q ENA D Q ENA D Q Write ENA Pulse Generator RAM/ROM 128 × 16 256 × 8 512 × 4 Data In 1,024 × 2 2,048 × 1 Data Out D Q ENA Read Address Write Address Read Enable Write Enable Altera Corporation To MegaLAB, FastTrack & Local Interconnect ...

Page 33

... All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset. (2) APEX 20KE devices have four dedicated clocks. Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Input/Output Clock Mode The input/output clock mode contains two clocks. One clock controls all registers for inputs into the ESB: data input, WE, RE, read address, and write address ...

Page 34

... When a match is found, a match flag is set high. diagram. RAM/ROM 128 × 16 256 × 8 512 × 4 Data In 1,024 × 2 2,048 × 1 Data Out D ENA Address Q Write Enable Write Pulse Generator Figure 23 shows the CAM block to MegaLAB, FastTrack & Q Local Interconnect Altera Corporation ...

Page 35

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 23. APEX 20KE CAM Block Diagram wraddress[] data[] wren inclock inclocken inaclr CAM can be used in any application requiring high-speed searches, such as networking, communications, data compression, and cache management. The APEX 20KE on-chip CAM provides faster system performance than traditional discrete CAM ...

Page 36

... An ESB is fed by the local interconnect, which is driven by adjacent LEs (for high-speed connection to the ESB) or the MegaLAB interconnect. The ESB can drive the local, MegaLAB, or FastTrack Interconnect routing structure to drive LEs and IOEs in the same MegaLAB structure or anywhere in the device. Figure 24 INCLKENA OUTCLKENA OUTCLOCK INCLR OUTCLR Altera Corporation ...

Page 37

... A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet TM option is available for ESBs that implement product-term ...

Page 38

... This feature is useful for cases where the APEX 20K device controls an active-low input or another device; it prevents inadvertent activation of the input upon power-up. Quartus II Logic Option Decrease input delay to internal cells Decrease input delay to input register Decrease input delay to output register Increase delay to output pin Figure 25 Altera Corporation shows ...

Page 39

... Dedicated Bus Inputs 2 Note to Figure 25: (1) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin. Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Note (1) VCC Chip-Wide Reset VCC Chip-Wide Output Enable OE[7..0] Input Pin to ...

Page 40

... Quartus II Logic Option Decrease input delay to internal cells Decrease input delay to input registers Decrease input delay to output register Increase delay to output pin Increase clock enable delay Figure 26 Altera Corporation ...

Page 41

... This programmable delay has four settings: off and three levels of delay. (2) The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin. Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Notes OE Register VCC Chip-Wide Reset ...

Page 42

... An LE can drive a pin through the local interconnect for faster clock-to-output times. shows how a row IOE connects to the MegaLAB Interconnect Each IOE can drive local, IOE MegaLAB, row, and column interconnect. Each IOE data and OE signal is driven by the local interconnect. IOE Altera Corporation ...

Page 43

... Any LE or ESB can drive a column pin through a row, column, and MegaLAB interconnect. Row Interconnect Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 28 shows how a column IOE connects to the interconnect. Each IOE can drive column interconnect. In APEX 20KE devices, IOEs can also drive FastRow interconnect ...

Page 44

... LVPECL, GTL+, CTT, HSTL Class I, SSTL-3 Class I and II, and SSTL-2 Class I and II. For more information on I/O standards supported by APEX 20KE devices, see Application Note 117 (Using Selectable I/O Standards in Altera Devices). The APEX 20KE device contains eight I/O banks. In QFP packages, the banks are linked to form four I/O banks ...

Page 45

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 29. APEX 20KE I/O Banks I/O Bank 1 I/O Bank 8 LVDS/LVPECL Output Block (2) (1) I/O Bank 7 I/O Bank 6 Notes to Figure 29: (1) For more information on placing I/O pins in LVDS blocks, refer to the Guidelines for Using LVDS Blocks section in Application Note 120 (Using LVDS in APEX 20KE Devices) ...

Page 46

... The rise time is dependent on the value of the pull- up resistor and load impedance. The I considered when selecting a pull-up resistor. level, input pins are 2.5-V, 3.3-V, and 5.0-V Output Signals (V) 5.0 2.5 v(1) v v(1) v(2) current specification should be OL Altera Corporation 3.3 5 ...

Page 47

... V, an APEX 20KE device can drive a 2.5-V device with 3.3-V tolerant inputs. CCIO ClockLock & ClockBoost Features Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet APEX 20KE devices also support the MultiVolt I/O interface feature. The APEX 20KE VCCINT pins must always be connected to a 1.8-V power supply. With a 1.8-V V CCINT tolerant ...

Page 48

... The clock can be multiplied by m/(n × m/(n × v), where m and k range from 2 to 160, and n and v range from 1 to 16. Clock multiplication and division can be used for time-domain multiplexing and other functions, which can reduce design LE requirements. Table 14 shows the Clock 2 ×1 ×2 ×4 Altera Corporation ...

Page 49

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Clock Phase & Delay Adjustment The APEX 20KE ClockShift feature allows the clock phase and delay to be adjusted. The clock phase can be adjusted by 90° steps. The clock delay can be adjusted to increase or decrease the clock delay by an arbitrary amount one clock period ...

Page 50

... The tI parameter refers to the nominal input clock period; the tO parameter refers to the nominal output clock period. Table 15 summarizes the APEX 20K ClockLock and ClockBoost parameters for -1 speed-grade devices. Parameter (2) INDUTY INCLKSTB JITTER O JITTER Min Max 25 180 25 180 25,000 Note ( CLKDEV Unit MHz (1) MHz MHz MHz % (3) PPM ns ns µs Altera Corporation ...

Page 51

... Jitter on ClockLock/ ClockBoost-generated clock JITTER t Input clock stability (measured between adjacent INCLKSTB clocks) Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Parameter is 250 ps. JITTER Table 16 summarizes the APEX 20K ClockLock and ClockBoost parameters for -2 speed grade devices. ...

Page 52

... ClockBoost to acquire lock 52 value is less than the time required for configuration. LOCK Tables 17 and 18 summarize the ClockLock and ClockBoost parameters for APEX 20KE devices. Conditions Note (1) Min Typ Max input period 0.35% of output period 45 Altera Corporation Unit peak-to- peak RMS % 55 40 µs ...

Page 53

... CLOCK1 for internal use f Output clock frequency for CLOCK0_EXT external clock0 output f Output clock frequency for CLOCK1_EXT external clock1 output Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet (Part I/O Standard -1X Speed Grade Min 200 1.5 20 3.3-V LVTTL 1.5 2 ...

Page 54

... Units Max 257 MHz 250 MHz 243 MHz 261 MHz 253 MHz 253 MHz 260 MHz 260 MHz 350 MHz Altera Corporation ...

Page 55

... The EP20K1500E device supports the JTAG BYPASS instruction and the SignalTap instructions. Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet All APEX 20K devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1-1990 specification. JTAG boundary-scan testing can be performed before or after configuration, but not during configuration ...

Page 56

... EP20K200E EP20K300E EP20K400 EP20K400E EP20K600E EP20K1000E EP20K1500E Note to Table 20: (1) This device does not support JTAG boundary scan testing. Tables 20 and 21 show the Boundary-Scan Register Length 420 624 786 774 984 1,176 1,164 1,266 1,536 1,506 1,806 2,190 1 (1) Altera Corporation ...

Page 57

... Signal to Be Captured t JSZX Signal to Be Driven Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet IDCODE (32 Bits) Part Number (16 Bits) 1000 0000 0011 0000 1000 0000 0110 0000 0000 0100 0001 0110 1000 0001 0000 0000 1000 0001 0110 0000 ...

Page 58

... AC test measurements for APEX 20K devices are made under conditions equivalent to those shown in Figure 32. Multiple test patterns can be used to configure devices during all stages of the production flow. Min Max Unit 100 Altera Corporation ...

Page 59

... DC output current, per pin OUT T Storage temperature STG T Ambient temperature AMB T Junction temperature J Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 32. APEX 20K AC Test Conditions Device Output C1 (includes Device input JIG capacitance) rise and fall times < Note to Figure ...

Page 60

... Note (2) Min Max 2.375 2.625 (2.375) (2.625) 3.00 (3.00) 3.60 (3.60) 2.375 2.625 (2.375) (2.625) –0.5 5. CCIO 0 85 –40 100 40 40 Notes (2), (7), Min Typ Max 5.75 CCIO 0.8, 0.3 × V CCIO (9) – 0.2 CCIO Altera Corporation Unit ° C ° (8) Unit ...

Page 61

... Tri-stated I/O pin leakage current supply current (standby) CC0 CC (All ESBs in power-down mode) R Value of I/O pin pull-up resistor CONF before and during configuration Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Conditions Min = 3.00 V (11) CCIO I = 0.1 mA DC, ...

Page 62

... OUT Notes to Tables 23 through 26: (1) See the Operating Requirements for Altera Devices Data Sheet. (2) All APEX 20K devices are 5.0-V tolerant. (3) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. ...

Page 63

... V Input voltage I V Output voltage O T Junction temperature J t Input rise time R t Input fall time F Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Conditions (3), (4) (3), (4) (3), (4) (3), (4) (5), (6) For commercial use For industrial use Min Max Unit 1 ...

Page 64

... CCIO V = 2.375 V (14) CCIO V = 1.71 V (14) CCIO (9) Typ Max 4.1 CCIO 0.8, 0.3 × V CCIO (10) 2.4 – 0.2 CCIO 2.1 2.0 1.7 0.4 0.2 0.1 × V CCIO 0.2 0.4 0.7 –10 10 – 150 Altera Corporation Unit µA µ kΩ kΩ kΩ ...

Page 65

... These values are specified under the APEX 20KE device recommended operating conditions, shown in Table 24 on page 60. (9) Refer to Application Note 117 (Using Selectable I/O Standards in Altera Devices) for the V parameters when VCCIO = 1.8 V. (10) The APEX 20KE input buffers are compatible with 1.8-V, 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. ...

Page 66

... CCINT Typical 2.5 V CCIO Output Room Temperature Current (mA Output Voltage (V) & V for 3.3-V PCI Compliance CCIO CCINT PCI-Compliant Region 3.1 3.3 V (V) CCIO . The output driver is compatible with CCIO Note ( Output Voltage ( 2.5 V CCINT V = 3.3 V CCIO Room Temperature Altera Corporation ...

Page 67

... Vo Output Voltage (V) Typical I O Output Current (mA) Note to Figure 35: (1) These are transient (AC) currents. Timing Model Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 35 shows the output drive characteristics of APEX 20KE devices CCINT = 1 CCIO = 3.3 V Room Temperature 1.5 2 ...

Page 68

... PTERMCO Figure 37 shows the f timing model for APEX 20KE devices. These MAX parameters can be used to estimate f Quartus II software timing analysis should be used for more accurate timing information. Routing Delay t F1—4 t F5—20 t F20+ for multiple levels of logic. MAX Altera Corporation ...

Page 69

... Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Figure 37. APEX 20KE f Timing Model MAX LUT ESB t ESBARC t ESBSRC t ESBAWC t ESBSWC t ESBWASU t ESBWDSU t ESBSRASU t ESBSWDSU t ESBWDH t ESBRASU t ESBRAH t ESBWESU t ESBWEH t ESBDATASU t ESBWADDRSU t ESBRADDRSU t ESBDATACO1 t ESBDATACO2 t ESBDD PTERMSU t PTERMCO Routing Delay t F1 – ...

Page 70

... Rdaddress a0 Data-Out d0 ESB Asynchronous Write WE Data-In t ESBWASU a0 Wraddress Data-Out 70 Figures 38 and 39 show the asynchronous and synchronous timing waveforms, respectively, for the ESB macroparameters ESBWP t ESBWDSU din0 t ESBWCCOMB a1 din0 Table a2 t ESBARC d2 t ESBWDH din1 t ESBWAH a2 t ESBDD din1 Altera Corporation 31 dout2 ...

Page 71

... WE Rdaddress a0 t ESBDATASU CLK Data-Out ESB Synchronous Write (ESB Output Registers Used) WE din1 Data- Wraddress t ESBWESU CLK Data-Out Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet a1 t ESBDATAH t ESBDATACO2 din2 a2 t ESBDATAH t ESBDATASU t ESBSWC dout0 dout1 Figure 40 shows the timing model for bidirectional I/O pin timing. ...

Page 72

... Table 31 describes the f MAX page 68. (Part (1) PRN t XZBIDIR ZXBIDIR CLRN t OUTCOBIDIR PRN CLRN IOE Register t (1) (2) PRN D Q CLRN timing parameters shown in Parameter Bidirectional Pin INSUBIDIR INHBIDIR Figure 36 on Altera Corporation ...

Page 73

... OUTCOBIDIR register t Synchronous IOE output buffer disable delay XZBIDIR t Synchronous IOE output buffer enable delay, slow slew rate = off ZXBIDIR Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet (Part Tables 32 and 33 describe APEX 20K external timing parameters. Note (1) Clock Parameter ...

Page 74

... ESB clock-to-output delay without output registers ESBDATACO2 t ESB data-in to data-out delay for RAM mode ESBDD t ESB Macrocell input to non-registered output PD t ESB Macrocell register setup time before clock PTERMSU t ESB Macrocell register clock-to-output delay PTERMCO timing model. MAX Parameter Parameter Altera Corporation ...

Page 75

... Hold time with PLL clock at IOE input register INHPLL t Clock-to-output delay with PLL clock at IOE output register OUTCOPLL Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Table 36. APEX 20KE Routing Timing Microparameters Symbol t Fanout delay using Local Interconnect F1-4 ...

Page 76

... Clock-to-output delay for bidirectional pins with PLL clock at IOE output OUTCOBIDIRPLL register t Synchronous Output Enable Register to output buffer disable delay with XZBIDIRPLL PLL t Synchronous Output Enable Register output buffer enable delay with PLL ZXBIDIRPLL Note to Tables 38 and 39: (1) These timing parameters are sample-tested only. 76 Note (1) Parameter Conditions Altera Corporation ...

Page 77

... CLRP t 0.5 PREP t 2.0 ESBCH t 2.0 ESBCL t 1.6 ESBWP t 1.0 ESBRP Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Tables 40 through 42 show the f EP20K200, and EP20K400 APEX 20K devices. -2 Speed Grade Max Min 0.6 0.8 0.3 0.8 1.7 5.7 3 ...

Page 78

... Units -3 Speed Grade Min Max 0.8 ns 1.0 ns 0.5 ns 1.3 ns 2.4 ns 8.1 ns 4.6 ns 3.1 ns 0.9 ns 3.3 ns 1.8 ns 3.6 ns 3.6 ns 3.6 ns 3.2 ns 2.1 ns 0.7 ns 1.8 ns 2.3 ns 3.0 ns 3.0 ns 0.4 ns 0.5 ns 3.0 ns 3.0 ns 2.2 ns 1.4 ns Altera Corporation ...

Page 79

... CL t 0.5 CLRP t 0.5 PREP t 2.0 ESBCH t 2.0 ESBCL t 1.5 ESBWP t 1.0 ESBRP Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min 0.3 0.8 0.1 1.0 1.7 5.7 3.9 2.7 0.8 2.9 1.3 2.5 2.5 2.5 2 ...

Page 80

... Min Max 3.2 ns 0.0 ns 2.0 6.6 ns – ns – ns – 4 Speed Grade Unit Min Max 3.2 ns 0.0 ns 2.0 6.6 ns 6.9 ns 6.9 ns – ns – ns – – ns – ns – Speed Grade Unit Min Max 2.6 ns 0.0 ns 2.0 6.8 ns – ns – ns – – ns Altera Corporation ...

Page 81

... INSUBIDIR t (2) 0.0 INHBIDIR t (2) 0.5 OUTCOBIDIR t (2) XZBIDIR t (2) ZXBIDIR Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min 2.3 0.0 4.6 2.0 5.0 5.0 1.2 0.0 2.7 0.5 4.3 4.3 -2 Speed Grade ...

Page 82

... Width Timing Parameters, External Timing Parameters, and External Bidirectional Timing Parameters for EP20K30E APEX 20KE devices. -2 Max Min 0.02 0.16 0.32 0.85 LE Timing Microparameters, f MAX Routing Delays, Minimum Pulse MAX -3 Max Min 0.02 0.23 0.45 1.20 Altera Corporation MAX Unit Max ns ns 0.67 ns 1.77 ns ...

Page 83

... ESBDD 1.04 PTERMSU t PTERMCO Table 51. EP20K30E f Routing Delays MAX Symbol -1 Min t F1-4 t F5-20 t F20+ Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -1 -2 Max Min 2.03 2.58 3.88 4.08 2.49 0.00 2.74 0.00 2.75 0.00 2.73 0.00 0.48 0.13 ...

Page 84

... Min Max 1.15 1.15 0.46 0.46 1.15 1.15 2.97 2.39 -3 Min Max 2.24 0.00 2.00 5. Max Min Max 1.54 0.00 5.36 2.00 5.88 8.46 9.83 8. 5.99 - 5.99 - Altera Corporation Unit Unit Unit ...

Page 85

... MAX Symbol -1 Min LUT Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Tables 55 through 60 describe f ESB Timing Microparameters, f Width Timing Parameters, External Timing Parameters, and External Bidirectional Timing Parameters for EP20K60E APEX 20KE devices. -2 Max Min 0.15 0.33 ...

Page 86

... Max Min Max 2.57 3.79 3.26 4.61 4.90 7.23 4.90 6.79 3.29 0.00 3.62 0.00 3.64 0.00 3.87 0.00 1.04 0.13 1.46 1.58 1.24 1.55 3.35 4.94 4.90 7.23 2.41 3.56 2.55 1.26 1.08 Altera Corporation Unit ...

Page 87

... ESBRP Table 59. EP20K60E External Timing Parameters Symbol -1 Min Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Max Min Max 0.24 0.26 1.45 1.58 1.96 2.14 -2 Max Min Max 2.50 2.50 0.28 0.28 2.50 2.50 1.80 1.45 ...

Page 88

... APEX 20KE devices. -2 Max Min Max 0.25 0.25 0.28 0.28 0.80 0.95 -3 Max Min Max 3.11 0.00 5.31 2.00 5.81 7.44 8.65 7. 5. Timing Microparameters, MAX Routing Delays, Minimum MAX -3 Min Max 0.25 0.25 0.34 1.13 Altera Corporation Unit Unit ...

Page 89

... ESBDD 1.11 PTERMSU t PTERMCO Table 63. EP20K100E f Routing Delays MAX Symbol -1 Min t F1-4 t F5-20 t F20+ Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -1 -2 Max Min 1.61 2.57 0.52 3.17 6.41 0.54 0.80 0.54 1.75 0.00 1.72 0.00 -0.20 0.13 ...

Page 90

... Min Max 2.00 2.00 0.20 0.20 2.00 2.00 1.66 1.41 -3 Min Max 2.43 0.00 2.00 5. Max Min Max 3.19 0.00 5.35 2.00 5.84 5.48 5.89 5. 3.42 - 3.42 - Altera Corporation Unit Unit Unit ...

Page 91

... MAX Symbol -1 Min LUT Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet Tables 67 through 72 describe f f ESB Timing Microparameters, f MAX Pulse Width Timing Parameters, External Timing Parameters, and External Bidirectional Timing Parameters for EP20K160E APEX 20KE devices. -2 Max ...

Page 92

... Max Min Max 2.02 2.11 2.70 3.11 3.79 4.42 3.56 4.10 0.73 0.47 0.94 0.47 2.06 0.01 2.00 0.00 0.09 0.13 0.35 0.43 1.30 1.46 2.70 3.16 3.35 3.97 1.93 2.29 1.52 1.32 1.04 Altera Corporation Unit ...

Page 93

... ESBRP Table 71. EP20K160E External Timing Parameters Symbol -1 Min Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Max Min Max 0.25 0.26 1.00 1.18 1.95 2.19 -2 Max Min Max 1.43 1.43 0.19 0.19 1.43 1.43 1.45 1.15 ...

Page 94

... Max Min 3.54 0.00 5.59 2.00 8.23 8. 3.35 - 5.99 5.99 LE Timing Microparameters, f MAX Routing Delays, Minimum Pulse MAX -3 Max Min 0.26 0.26 0.31 0.90 Unit Max ns ns 6.13 ns 8. MAX Unit Max ns ns 0.36 ns 1.14 ns Altera Corporation ...

Page 95

... ESBDD 1.00 PTERMSU t PTERMCO Table 75. EP20K200E f Routing Delays MAX Symbol -1 Min t F1-4 t F5-20 t F20+ Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -1 -2 Max Min 1.68 2.27 3.10 2.90 0.67 0.46 0.83 0.46 1.90 0.00 1.71 0.00 -0.07 0.13 ...

Page 96

... Max 2.44 2.44 0.19 0.19 2.44 2.44 1.48 1.17 -2 Max Min Max 2.35 0.00 5.12 2.00 5.62 2.07 0.00 3.01 0.50 3.36 -3 Unit Min Max 2.65 ns 2.65 ns 0.21 ns 0.21 ns 2.65 ns 2.65 ns 1. Unit Min Max 2.47 ns 0.00 ns 2.00 6. Altera Corporation ...

Page 97

... Table 79. EP20K300E f LE Timing Microparameters MAX Symbol -1 Min LUT Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -1 Max Min 3.19 0.00 5.12 2.00 7.51 7.51 3.64 0.00 3.01 0.50 5.40 5.40 Tables 79 through 84 describe f ESB Timing Microparameters, f Width Timing Parameters, External Timing Parameters, and External Bidirectional Timing Parameters for EP20K300E APEX 20KE devices ...

Page 98

... Max Min 2.44 3.12 4.65 4.68 2.83 0.00 3.11 0.00 3.13 0.00 3.28 0.00 0.80 0.13 1.17 1.28 1.20 3.18 4.65 2.29 2.14 1.22 -3 Max Min 0.24 1.43 3.93 Altera Corporation Unit Max 3.25 ns 4.01 ns 6. 1.40 ns 4.24 ns 6.20 ns 3.06 ...

Page 99

... Table 84. EP20K300E External Bidirectional Timing Parameters Symbol Min Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Max Min Max 1.43 1.43 0.26 0.26 1.43 1.43 1.71 1.38 -2 Max Min Max 2.44 0.00 5.29 2.00 5.82 1.85 0.00 2.65 0.50 2.95 -1 ...

Page 100

... Width Timing Parameters, External Timing Parameters, and External Bidirectional Timing Parameters for EP20K400E APEX 20KE devices. -2 Speed Grade Max Min 0.23 0.23 0.25 0.70 LE Timing Microparameters, f MAX Routing Delays, Minimum Pulse MAX -3 Speed Grade Max Min 0.23 0.23 0.29 0.83 Altera Corporation MAX Unit Max ns ns 0.32 ns 1.01 ns ...

Page 101

... ESBDATAH t -0.02 ESBWADDRSU t 0.06 ESBRADDRSU t ESBDATACO1 t ESBDATACO2 t ESBDD 0.92 PTERMSU t PTERMCO Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 1.67 1.91 2.30 2.66 3.09 3.58 3.01 3.65 0.63 0.43 0.77 0.43 1.77 0.00 1.47 ...

Page 102

... Speed Grade Unit Min Max 0.26 ns 1. Speed Grade Unit Min Max 2.35 ns 2.35 ns 0.19 ns 0.19 ns 2.35 ns 2.35 ns 1. Speed Grade Unit Min Max 2.77 ns 0.00 ns 2.00 6. Altera Corporation ...

Page 103

... Table 91. EP20K600E f LE Timing Microparameters MAX Symbol -1 Speed Grade Min LUT Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min 3.23 0.00 5.25 2.00 5.95 5.95 4.76 0.00 2.25 0.50 2.94 2.94 Tables 91 through 96 describe f ...

Page 104

... Speed Grade Min Max 0.26 1.52 4.26 Altera Corporation Unit Unit ...

Page 105

... Min Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 2.50 2.50 0.26 0.26 2.50 2.50 1.68 1.35 -2 Speed Grade Max Min Max 2.74 0.00 5.51 2.00 6.06 1.96 0.00 2.62 0.50 2 ...

Page 106

... Bidirectional Timing Parameters for EP20K1000E APEX 20KE devices. LE Timing Microparameters -2 Speed Grade Max Min 0.25 0.25 0.28 0.80 LE Timing Microparameters, f MAX Routing Delays, Minimum Pulse MAX -3 Speed Grade Max Min 0.25 0.25 0.32 0.95 Altera Corporation MAX Unit Max ns ns 0.33 ns 1.13 ns ...

Page 107

... ESBWADDRSU t 0.14 ESBRADDRSU t ESBDATACO1 t ESBDATACO2 t ESBDD 1.08 PTERMSU t PTERMCO Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet ESB Timing Microparameters -2 Speed Grade Max Min 1.78 2.52 3.52 3.23 0.67 0.55 0.79 0.55 1.92 0.01 2.28 0.00 0.27 0.13 ...

Page 108

... Speed Grade Max Min 0.27 1.63 4.33 -3 Speed Grade Max Min 1.67 1.67 0.20 0.20 1.67 1.67 1.65 1.41 -3 Speed Grade Max Min 2.97 0.00 6.33 2. 2.99 - Altera Corporation Unit Max 0.27 ns 1.75 ns 4.97 ns Unit Max Unit Max ...

Page 109

... Table 103. EP20K1500E f MAX Symbol -1 Speed Grade Min LUT Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min 3.33 0.00 5.75 2.00 6.31 6.31 3.26 0.00 2.25 0.50 2.81 2.81 Tables 103 through 108 describe f ...

Page 110

... Min 2.02 2.91 4.11 3.84 0.61 0.55 0.81 0.55 1.85 0.23 2.41 0.00 0.29 0.13 0.11 0.16 1.50 2.99 3.57 2.13 1.32 1.53 -3 Speed Grade Max Min 0.28 1.50 4.48 Altera Corporation Unit Max 1.95 ns 3.14 ns 4. 1.63 ns 3. ...

Page 111

... Table 107. EP20K1500E External Timing Parameters Symbol -1 Speed Grade Min Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet -2 Speed Grade Max Min Max 1.43 1.43 0.20 0.20 1.43 1.43 1.51 1.29 -2 Speed Grade Max Min Max 3.30 0.00 6.18 2.00 6 ...

Page 112

... Speed Grade Max Min Max 0.00 0.00 0.00 0.00 0.04 0.05 0.03 0.04 0.09 0.10 –0.19 –0.47 0.03 –0.23 –0.32 –0.31 –0.12 0.00 0.00 0.00 0.00 Altera Corporation Unit Unit Min ...

Page 113

... To estimate device power consumption, use the interactive power calculator on the Altera web site at http://www.altera.com. The APEX 20K architecture supports several configuration schemes. This section summarizes the device operating modes and available device configuration schemes. Operating Modes The APEX architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up ...

Page 114

... MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam or JBC File For more information on configuration, see Application Note 116 (Configuring APEX 20K, FLEX 10K, & FLEX 6000 Devices.) See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin-out information Table 111), chosen on the basis ...

Page 115

... Revision History Altera Corporation APEX 20K Programmable Logic Device Family Data Sheet The information contained in the APEX 20K Programmable Logic Device Family Data Sheet version 5.1 supersedes information published in previous versions. Version 5.1 APEX 20K Programmable Logic Device Family Data Sheet version 5.1 contains the following changes: ■ ...

Page 116

... Version 4.1 APEX 20K Programmable Logic Device Family Data Sheet version 4.1 contains the following changes: ■ t added to Figure 37 ESBWEH 92, 97, and 104. ■ Updated EP20K300E device internal and external timing numbers in Tables 79 through 84. and Tables 35, 50, 56, 62, 68, 74, 86, Altera Corporation ...

Page 117

... Copyright © 2004 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U ...

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