EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 9

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Altera Corporation
Functional
Description
Figure 1. APEX 20K Device Block Diagram
Four-input LUT
for data path and
DSP functions.
Product-term
integration for
high-speed
control logic and
state machines.
Clock Management Circuitry
ClockLock
IOE
IOE
Product Term
Product Term
APEX 20K devices incorporate LUT-based logic, product-term-based
logic, and memory into one device. Signal interconnections within
APEX 20K devices (as well as to and from device pins) are provided by the
FastTrack
channels that run the entire length and width of the device.
Each I/O pin is fed by an I/O element (IOE) located at the end of each row
and column of the FastTrack Interconnect. Each IOE contains a
bidirectional I/O buffer and a register that can be used as either an input
or output register to feed input, output, or bidirectional signals. When
used with a dedicated clock pin, these registers provide exceptional
performance. IOEs provide a variety of features, such as 3.3-V, 64-bit,
66-MHz PCI compliance; JTAG BST support; slew-rate control; and
tri-state buffers. APEX 20KE devices offer enhanced I/O support,
including support for 1.8-V I/O, 2.5-V I/O, LVCMOS, LVTTL, LVPECL,
3.3-V PCI, PCI-X, LVDS, GTL+, SSTL-2, SSTL-3, HSTL, CTT, and 3.3-V
AGP I/O standards.
The ESB can implement a variety of memory functions, including CAM,
RAM, dual-port RAM, ROM, and FIFO functions. Embedding the
memory directly into the die improves performance and reduces die area
compared to distributed-RAM implementations. Moreover, the
abundance of cascadable ESBs ensures that the APEX 20K device can
implement multiple wide memory blocks for high-density designs. The
ESB’s high speed ensures it can implement small memory blocks without
any speed penalty. The abundance of ESBs ensures that designers can
create as many different-sized memory blocks as the system requires.
Figure 1
Memory
Memory
LUT
IOE
LUT
IOE
shows an overview of the APEX 20K device.
®
Product Term
Product Term
Interconnect—a series of fast, continuous row and column
Memory
Memory
LUT
LUT
IOE
IOE
APEX 20K Programmable Logic Device Family Data Sheet
Product Term
Product Term
Memory
Memory
LUT
LUT
IOE
IOE
Product Term
Product Term
Memory
Memory
LUT
LUT
IOE
IOE
FastTrack
Interconnect
IOE
IOE
LUT
Flexible integration
of embedded
memory, including
CAM, RAM,
ROM, FIFO, and
other memory
functions.
IOEs support
PCI, GTL+,
SSTL-3, LVDS,
and other
standards.
9