EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 13

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Altera Corporation
Figure 5. APEX 20K Logic Element
labclkena2
data1
data2
data3
data4
Chip-Wide
labclkena1
labclk1
labclk2
labclr1
labclr2
Reset
Look-Up
Asynchronous
Clear/Preset/
(LUT)
Table
Load Logic
Clock &
Clock Enable
Select
Carry-Out
Carry-In
Chain
Carry
Logic Element
The LE, the smallest unit of logic in the APEX 20K architecture, is compact
and provides efficient logic usage. Each LE contains a four-input LUT,
which is a function generator that can quickly implement any function of
four variables. In addition, each LE contains a programmable register and
carry and cascade chains. Each LE drives the local interconnect, MegaLAB
interconnect, and FastTrack Interconnect routing structures. See
Each LE’s programmable register can be configured for D, T, JK, or SR
operation. The register’s clock and clear control signals can be driven by
global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the register is bypassed and the output of the
LUT drives the outputs of the LE.
Cascade-In
Cascade
Chain
Cascade-Out
Synchronous
LAB-wide
Load
Synchronous
Load & Clear
Logic
APEX 20K Programmable Logic Device Family Data Sheet
Synchronous
LAB-wide
Clear
D
ENA
CLRN
PRN
Register Bypass
Packed
Register Select
Q
Register
Programmable
To F astTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
To F astTrack Interconnect,
MegaLAB Interconnect,
or Local Interconnect
Figure
13
5.