EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 52

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APEX 20K Programmable Logic Device Family Data Sheet
52
Notes to
(1)
(2)
(3)
(4)
t
t
t
t
t
t
t
OUTJITTER
OUTDUTY
LOCK
Table 17. APEX 20KE ClockLock & ClockBoost Parameters
R
F
INDUTY
INJITTER
Symbol
To implement the ClockLock and ClockBoost circuitry with the Quartus II software, designers must specify the
input frequency. The Quartus II software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The f
device operation. Simulation does not reflect this parameter.
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the t
The t
(2)
Table
,
CLKDEV
JITTER
(3)
16:
specification is measured under long-term observation.
Input rise time
Input fall time
Input duty cycle
Input jitter peak-to-peak
Jitter on ClockLock or ClockBoost-
generated clock
Duty cycle for ClockLock or
ClockBoost-generated clock
Time required for ClockLock or
ClockBoost to acquire lock
parameter specifies how much the incoming clock can differ from the specified frequency during
Parameter
Tables 17
for APEX 20KE devices.
LOCK
value is less than the time required for configuration.
and
18
summarize the ClockLock and ClockBoost parameters
Conditions
Note (1)
Min
40
45
Typ
output period
2% of input
Altera Corporation
0.35% of
period
Max
60
55
40
5
5
peak-to-
RMS
Unit
peak
µs
ns
ns
%
%