EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 62

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

APEX 20K Programmable Logic Device Family Data Sheet
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10) The I
(11) The I
(12) This value is specified for normal device operation. The value may vary during power-up.
(13) Pin pull-up resistance values will be lower if an external source drives the pin higher than V
(14) Capacitance is sample-tested only.
62
C
C
C
V
V
V
I
T
T
T
Symbol
Symbol
Table 26. APEX 20K 5.0-V Tolerant Device Capacitance
Table 27. APEX 20KE Device Absolute Maximum Ratings
OUT
IN
INCLK
OUT
STG
AMB
J
CCINT
CCIO
I
See the Operating Requirements for Altera Devices Data Sheet.
All APEX 20K devices are 5.0-V tolerant.
Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.75 V for
input currents less than 100 mA and periods shorter than 20 ns.
Numbers in parentheses are for industrial-temperature-range devices.
Maximum V
All pins, including dedicated inputs, clock I/O, and JTAG pins, may be driven before V
powered.
Typical values are for T
These values are specified in the APEX 20K device recommended operating conditions, shown in Table 26 on
page 62.
The APEX 20K input buffers are compatible with 2.5-V and 3.3-V (LVTTL and LVCMOS) signals. Additionally, the
input buffers are 3.3-V PCI compliant when V
as well as output pins.
Tables 23
OH
OL
Input capacitance
Input capacitance on dedicated
clock pin
Output capacitance
Supply voltage
DC input voltage
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
parameter refers to low-level TTL, PCI, or CMOS output current. This parameter applies to open-drain pins
parameter refers to high-level TTL, PCI or CMOS output current.
CC
Parameter
through 26:
Parameter
rise time is 100 ms, and V
A
= 25
Tables 27
recommended operating conditions, DC operating conditions, and
capacitance for 1.8-V APEX 20KE devices.
° C, V
CCINT
V
V
V
With respect to ground
No bias
Under bias
PQFP, RQFP, TQFP, and BGA packages,
under bias
Ceramic PGA packages, under bias
through
IN
IN
OUT
= 2.5 V, and V
CC
= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz
= 0 V, f = 1.0 MHz
must rise monotonically.
CCIO
30
and V
provide information on absolute maximum ratings,
CCIO
Conditions
Conditions
CCINT
= 2.5 or 3.3 V.
(2)
Notes
meet the relationship shown in Figure 33 on page 68.
Note (1)
(2),
(14)
Min
Min
–0.5
–0.5
–0.5
–25
–65
–65
CCINT
CCIO
Altera Corporation
and V
.
Max
Max
150
135
135
150
2.5
4.6
4.6
CCIO
12
25
8
8
are
Unit
Unit
mA
° C
° C
° C
° C
pF
pF
pF
V
V
V