EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 51

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes to
(1)
(2)
(3)
(4)
(5)
Altera Corporation
t
t
t
f
f
f
f
t
f
t
t
t
t
t
t
SKEW
JITTER
INCLKSTB
OUT
R
Table 15. APEX 20K ClockLock & ClockBoost Parameters for -1 Speed-Grade Devices (Part 2 of 2)
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade Devices
CLK1
CLK2
CLK4
OUTDUTY
CLKDEV
F
LOCK
SKEW
JITTER
INCLKSTB
Symbol
Symbol
The PLL input frequency range for the EP20K100-1X device for 1x multiplication is 25 MHz to 175 MHz.
All input clock specifications must be met. The PLL may not lock onto an incoming clock if the clock specifications
are not met, creating an erroneous clock within the device.
During device configuration, the ClockLock and ClockBoost circuitry is configured first. If the incoming clock is
supplied during configuration, the ClockLock and ClockBoost circuitry locks during configuration, because the lock
time is less than the configuration time.
The jitter specification is measured under long-term observation.
If the input clock stability is 100 ps, t
Table
15:
Skew delay between related
ClockLock/ClockBoost-generated clocks
Jitter on ClockLock/ClockBoost-generated clock
(5)
Input clock stability (measured between adjacent
clocks)
Output frequency
Input clock frequency (ClockBoost clock multiplication
factor equals 1)
Input clock frequency (ClockBoost clock multiplication
factor equals 2)
Input clock frequency (ClockBoost clock multiplication
factor equals 4)
Duty cycle for ClockLock/ClockBoost-generated clock
Input deviation from user specification in the Quartus II
software (ClockBoost clock multiplication factor equals
one)
Input rise time
Input fall time
Time required for ClockLock/ ClockBoost to acquire
lock
Skew delay between related ClockLock/ ClockBoost-
generated clock
Jitter on ClockLock/ ClockBoost-generated clock
Input clock stability (measured between adjacent
clocks)
(3)
(1)
Table 16
parameters for -2 speed grade devices.
Parameter
Parameter
JITTER
summarizes the APEX 20K ClockLock and ClockBoost
is 250 ps.
APEX 20K Programmable Logic Device Family Data Sheet
(4)
Min
Min
500
25
25
16
10
40
25,000
Max
Max
500
200
170
170
500
200
50
80
34
60
10
50
5
5
(2)
Unit
MHz
MHz
MHz
MHz
Unit
PPM
ps
ps
ps
ns
ns
µs
ps
ps
ps
%
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