EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 35

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Altera Corporation
Figure 23. APEX 20KE CAM Block Diagram
CAM can be used in any application requiring high-speed searches, such
as networking, communications, data compression, and cache
management.
The APEX 20KE on-chip CAM provides faster system performance than
traditional discrete CAM. Integrating CAM and logic into the APEX 20KE
device eliminates off-chip and on-chip delays, improving system
performance.
When in CAM mode, the ESB implements 32-word, 32-bit CAM. Wider or
deeper CAM can be implemented by combining multiple CAMs with
some ancillary logic implemented in LEs. The Quartus II software
combines ESBs and LEs automatically to create larger CAMs.
CAM supports writing “don’t care” bits into words of the memory. The
“don’t-care” bit can be used as a mask for CAM comparisons; any bit set
to “don’t-care” has no effect on matches.
The output of the CAM can be encoded or unencoded. When encoded, the
ESB outputs an encoded address of the data’s location. For instance, if the
data is located in address 12, the ESB output is 12. When unencoded, the
ESB uses its 16 outputs to show the location of the data over two clock
cycles. In this case, if the data is located in address 12, the 12th output line
goes high. When using unencoded outputs, two clock cycles are required
to read the output because a 16-bit output bus is used to show the status
of 32 words.
The encoded output is better suited for designs that ensure duplicate data
is not written into the CAM. If duplicate data is written into two locations,
the CAM’s output will be incorrect. If the CAM may contain duplicate
data, the unencoded output is a better solution; CAM with unencoded
outputs can distinguish multiple data locations.
CAM can be pre-loaded with data during configuration, or it can be
written during system operation. In most cases, two clock cycles are
required to write each word into CAM. When “don’t-care” bits are used,
a third clock cycle is required.
APEX 20K Programmable Logic Device Family Data Sheet
wraddress[]
data[]
wren
inclock
inclocken
inaclr
data_address[]
outclocken
outclock
outaclr
match
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