EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 25

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Altera Corporation
Note to
(1)
Row I/O Pin
Column I/O
Pin
LE
ESB
Local
Interconnect
MegaLAB
Interconnect
Row
FastTrack
Interconnect
Column
FastTrack
Interconnect
FastRow
Interconnect
Table 9. APEX 20K Routing Scheme
Source
This connection is supported in APEX 20KE devices only.
Table
9:
I/O Pin
Row
v
Column
I/O Pin
v
Product-Term Logic
The product-term portion of the MultiCore architecture is implemented
with the ESB. The ESB can be configured to act as a block of macrocells on
an ESB-by-ESB basis. Each ESB is fed by 32 inputs from the adjacent local
interconnect; therefore, it can be driven by the MegaLAB interconnect or
the adjacent LAB. Also, nine ESB macrocells feed back into the ESB
through the local interconnect for higher performance. Dedicated clock
pins, global signals, and additional inputs from the local interconnect
drive the ESB control signals.
In product-term mode, each ESB contains 16 macrocells. Each macrocell
consists of two product terms and a programmable register.
shows the ESB in product-term mode.
v
LE
ESB
v
Interconnect
APEX 20K Programmable Logic Device Family Data Sheet
Local
(1)
v
v
v
v
v
Destination
Interconnect
MegaLAB
v
v
v
v
v
Interconnect
FastTrack
Row
v
v
v
v
Interconnect
FastTrack
Column
v
v
v
v
v
Figure 13
Interconnect
FastRow
(1)
v
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