EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 29
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EP20K100EFC324-2
Manufacturer Part Number
EP20K100EFC324-2
Description
IC APEX 20KE FPGA 100K 324-FBGA
Manufacturer
Altera
Series
APEX-20K®r
Datasheet
1.EP20K30ETC144-3.pdf
(117 pages)
Specifications of EP20K100EFC324-2
Number Of Logic Elements/cells
4160
Number Of Labs/clbs
416
Total Ram Bits
53248
Number Of I /o
246
Number Of Gates
263000
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Family Name
APEX 20K
Number Of Usable Gates
100000
Number Of Logic Blocks/elements
4160
# Registers
26
# I/os (max)
246
Frequency (max)
250MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.8V
Logic Cells
4160
Ram Bits
53248
Device System Gates
263000
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (max)
1.89V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP20K100EFC324-2
Manufacturer:
ALTERA
Quantity:
18
Company:
Part Number:
EP20K100EFC324-2
Manufacturer:
PANASONIC
Quantity:
86
Company:
Part Number:
EP20K100EFC324-2
Manufacturer:
ALTERA
Quantity:
25
Company:
Part Number:
EP20K100EFC324-2-3
Manufacturer:
VISHAY
Quantity:
15 000
Company:
Part Number:
EP20K100EFC324-2X
Manufacturer:
ALTERA
Quantity:
15
Altera Corporation
Figure 16. APEX 20K Parallel Expanders
Embedded
System Block
Local Interconnect
32 Signals from
The ESB can implement various types of memory blocks, including
dual-port RAM, ROM, FIFO, and CAM blocks. The ESB includes input
and output registers; the input registers synchronize writes, and the
output registers can pipeline designs to improve system performance. The
ESB offers a dual-port mode, which supports simultaneous reads and
writes at two different clock frequencies.
diagram.
Figure 17. ESB Block Diagram
Product-
Product-
Select
Select
Matrix
Matrix
Term
Term
APEX 20K Programmable Logic Device Family Data Sheet
wraddress[]
data[]
wren
inclock
inclocken
inaclr
Parallel
Expander Switch
Parallel
Expander Switch
Macrocell
Previous
From
Macrocell
Figure 17
To Next
rdaddress[]
outclocken
outclock
outaclr
rden
shows the ESB block
q[]
Macrocell
Product-
Term Logic
Macrocell
Product-
Term Logic
29