EP20K100EFC324-2 Altera, EP20K100EFC324-2 Datasheet - Page 3

• Manufacturer Part Number: EP20K100EFC324-2
• Description: IC APEX 20KE FPGA 100K 324-FBGA
• Manufacturer: Altera
• Series: APEX-20K®r

Specifications of EP20K100EFC324-2

• Number Of Logic Elements/cells: 4160
• Number Of Labs/clbs: 416
• Total Ram Bits: 53248
• Number Of I /o: 246
• Number Of Gates: 263000
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-FBGA
• Family Name: APEX 20K
• Number Of Usable Gates: 100000
• Number Of Logic Blocks/elements: 4160
• # Registers: 26
• # I/os (max): 246
• Frequency (max): 250MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.8V
• Logic Cells: 4160
• Ram Bits: 53248
• Device System Gates: 263000
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (max): 1.89V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 324
• Package Type: FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Altera Corporation
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Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
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Powerful I/O features
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Advanced interconnect structure
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Advanced packaging options
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Advanced software support
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Built-in low-skew clock tree
Up to eight global clock signals
ClockLock
ClockBoost
ClockShift
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2 for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
Bidirectional I/O performance (t
LVDS performance up to 840 Mbits per channel
Direct connection from I/O pins to local interconnect providing
fast t
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see
Programmable clamp to V
Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce switching
noise
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
Pull-up on I/O pins before and during configuration
Four-level hierarchical FastTrack
providing fast, predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
Available in a variety of packages with 144 to 1,020 pins (see
Tables 4
FineLine BGA
Software design support and automatic place-and-route
provided by the Altera
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APEX 20K Programmable Logic Device Family Data Sheet
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feature reducing clock delay and skew
feature providing clock multiplication and division
programmable clock phase and delay shifting
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packages maximize board space efficiency
times for complex logic
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Quartus
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II development system for
Interconnect structure
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